Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies

Gavaskar, K.; Dhivya, R.; Dayana, R.

doi:10.1007/s11277-022-09654-6

Cited by 6 publications

(1 citation statement)

References 19 publications

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“…For ECG data, the sampling rate is usually in the region of several hundred hertz [5], [38], [43]. Considering, the possible clock frequency in CMOS technology, i.e., up to several gigahertz [44], the discrepancy of multiple orders of magnitude already indicates duty-cycling of the digital backend, when the number of operations for classification is low. Then, frames of size N frame from the Fig.…”

Section: Algorithm-hardware Codesign Methodology For Streaming Ecg Mo...mentioning

confidence: 99%

Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers

Loh,

Gemmeke

2024

IEEE Trans. VLSI Syst.

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Monitoring of biomedical data, such as electrocardiogram (ECG) signals, requires accelerators, which can process data streams in a continuous manner. Especially, wearable monitoring systems require both ultralow power consumption and sufficiently complex deep neural network (DNN) classifiers to identify asymptomatic and critical health conditions, such as atrial fibrillation (AF). Such continuous data streams pose unique constraints on the processing pipeline for classification systems, which can be addressed in the design methodology of application-specific integrated circuits (ASICs). In this work, we identify specific constraints to define common operating conditions, which guide the design of ECG accelerators in an algorithm-hardware codesign methodology. In specific, we show that the input frame size and the number of classifications per time frame play a significant role for the computational complexity (CC) of the classifier, as well as the ECG accelerator executing the classifier in a continuous manner. As an example, the constraints are applied in a top-down algorithm-hardware codesign flow. Here, an ECG accelerator is designed starting from an AF classifier, while proposed constraints are considered in an early design stage to estimate costs for the hardware design. In the end, it is essential for future ECG accelerators to adhere to common constraints in the design process to handle increasingly complex DNN classifiers for continuous data streams with ultralow power targets.

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Section: Algorithm-hardware Codesign Methodology For Streaming Ecg Mo...mentioning

confidence: 99%

Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers

Loh,

Gemmeke

2024

IEEE Trans. VLSI Syst.

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A Variant of Long Multiplication Design with Low Power and Area Using Modified 7:3 Compressor for Biomedical Applications

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2022

Wireless Pers Commun

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Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2022

Wireless Pers Commun

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Multiplication is one of the basic functions in Digital Signal Processing (DSP) applications. Multiplier plays an important role in Arithmetic and Logic Unit (ALU), which is a critical element in the processors. The e ciency of the multiplier takes part a crucial task in the execution of the processor. The performance of the multiplier depends on the adder circuit. The addition operation is the fundamental operation used in most of the digital circuits. Power, delay and area are the main issues in VLSI circuits. E ciency of a VLSI circuit can be improved by rectifying any of these issues. Quaternary Signed Digits (QSD) placed on adders have better e ciency when compared to traditional binary logic. QSD based Carry Look Ahead (CLA) Adder is used to increase the e ciency with reference to power and delay. The proposed method uses Quaternary Carry Increment Adder in order to improve the power and reduce the delay of the existing Quaternary Carry Look Ahead Adder. Tanner EDA is the simulation tool used to design the circuits and the power, delay and power-delay product of the designed circuits are measured using it.

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Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies

Cited by 6 publications

References 19 publications

Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers

Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers

A Variant of Long Multiplication Design with Low Power and Area Using Modified 7:3 Compressor for Biomedical Applications

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

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