A Fast-Lock Analog Multiphase Delay-Locked Loop Using a Dual-Slope Technique

Chen, Pin-Tseng; Chang, Chia-Chen; Liu, Han-Ying; Lo, Yu-Lung

doi:10.1109/is3c.2012.249

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…Delay locked loops (DLLs) are typically used as multiphase clock generator and also to stabilize the timing information in TDC due to PVT variations [8]. The analog DLL consist of phase detector (PD), charge pump (CP), loop filter (LF) and voltage controlled delay line (VCDL) [9]. The architecture proposed in [10] offers better jitter performance and VCDL provides acceptable power supply rejection ratio (PSRR).…”

Section: Introductionmentioning

confidence: 99%

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

et al. 2020

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This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). In the lock state, the ACC value dithers due to the closed loop operation. A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. It helps the jitter reduction in the ADDLL. Additionally, it provides robustness against glitches, false locking and unlocking in a noisy environment. The ADDLL peak to peak jitter and RMS jitter at 625 MHz are 6.5 ps and 1.2 ps respectively. The ADDLL including DCDC is implemented on 0.18 µm CMOS technology with an operational range of 350∼900 MHz. It consumes only 6.8 mW at 625 MHz power with 1.8 V power supply. The area utilization is 0.06 mm 2. INDEX TERMS All digital delay locked loop (ADDLL), digital controller, jitter, light detection and ranging (LIDAR), time to digital converter (TDC).

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Section: Introductionmentioning

confidence: 99%

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

et al. 2020

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“…On the other hand, the DLL using the VCDL instead of the VCO does not accumulate over many clock cycles therefore, DLL exhibits better jitter performance than PLL. In addition, DLL have smaller area and faster locking time than the PLL [1]. Low power, wide lock range, short locking time, and low jitter are focuses of the DLL design.…”

Section: Introductionmentioning

confidence: 99%

A Fast-Lock Low-Jitter DLL with Double Edge Synchronization in 0.18µm CMOS Technology

Mohaghegh

2014

BJAST

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Aims: This paper describes a fast-lock, low-power, low-jitter and good duty-cycle correction capability delay locked loop with double edge synchronization which is mainly used in clock alignment process. A clock aligner's task is to phase-align a chip internal clock with a reference clock. The main advantage of delay locked loop rather than phase locked loop is related to good jitter performance of it. Double edge synchronization method leads to more power consumption and it can increase rms and peak-to-peak jitter therefore, in this work rms jitter, peak-to-peak jitter and power consumption are implemented to understand if this statement is always true or not. So, this case became one of our aims. Study Design: Double edge synchronization delay locked loop. Place and Duration of Study: Department of Electrical Engineering (Islamic Azad University, Central Tehran Branch), between February 2012 and September 2012.Methodology: Comparing with single edge synchronization delay locked loops, double edge synchronization method has its own advantages and disadvantages. Using two phase frequency detectors, two charge pumps and two loop filters in double edge delay locked loops, increases the jitter and power consumption. In this paper, to overcome these challenges for the introduced delay locked loop circuit, proper blocks with suitable characteristic for each MOSFET were used which took a lot of time to find ones with the help of HSPICE simulator. Results: All the simulation results are based on 0.18μm CMOS technology with 1.8V

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A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique

Fan

Wang

et al. 2018

Microsyst Technol

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A Fast-Lock Analog Multiphase Delay-Locked Loop Using a Dual-Slope Technique

Cited by 4 publications

References 10 publications

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

A Fast-Lock Low-Jitter DLL with Double Edge Synchronization in 0.18µm CMOS Technology

A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique

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