A fast algorithm for or-and-or synthesis

Debnath, Debatosh; Vranesic, Z.G.

doi:10.1109/tcad.2003.816216

Cited by 17 publications

(11 citation statements)

References 25 publications

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“…The drawbacks of this approach are the unbounded number of levels (and therefore the longer delay), as well as the much larger computational time required to synthesize the network. In an attempt to establish an effective trade-off between these two opposite approaches, recent studies have proposed the optimization of networks with a fixed number of levels (typically, three or four) [4], [5], [6], [7]. Sasao statistically showed that three levels of logic are enough to produce a minimal network for most of the Boolean functions; and in many cases threelevel logic is a good compromise between circuit speed, circuit size, and minimization time [8].…”

Section: Introductionmentioning

confidence: 99%

EXOR Projected Sum of Products

Bernasconi

Ciriani

Cordone

2006

2006 IFIP International Conference on Very Large Scale Integration

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In this paper we introduce a new algebraic form for Boolean function representation, called EXOR-Projected Sum of Products (EP-SOP), resulting in a four level network that can be easily implemented in practice. We prove that deriving an optimal EP-SOP from an optimal Sum of Products (SOP) form is a hard problem (NPNP-hard); nevertheless we propose a very efficient approximation algorithm, which returns in polynomial time an EP-SOP form whose cost is guaranteed to be near the optimum. Experimental evidence shows that for about 35% of the classical synthesis benchmarks the EP-SOP networks have a smaller area and delay with respect to the optimal SOPs (sometimes gaining even 40-50% of the area). Since the computational times required are extremely short, we recommend the use of the proposed approach as a post-processing step after SOP minimization

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Section: Introductionmentioning

confidence: 99%

EXOR Projected Sum of Products

Bernasconi

Ciriani

Cordone

2006

2006 IFIP International Conference on Very Large Scale Integration

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“…A different pairing algorithm targeting EX-SOPs may lead to better solutions. Investigations are underway for integrating the proposed AND-OR-EXOR design techniques with three-level OR-AND-OR synthesis methods [8] and for adapting the integrated design systems to synthesize logic circuits for commercial CPLDs that have four-level OR-AND-OR-EXOR architecture [2]. Logic synthesis for such a four-level architecture is a challenging problem and very little has been published on the topic [27].…”

Section: Conclusion and Commentsmentioning

confidence: 99%

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

Debnath

Sasao

2005

IEICE Transactions on Information and Systems

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Debatosh DEBNATH †a) , Nonmember and Tsutomu SASAO † †b) , Member SUMMARY This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-ofproducts expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EXSOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMINlike algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3 · 2 n−2 + 7n − 5 products in an EX-SOP while it is known that a sum-of-products expression (SOP) requires 6 · 2 n − 4n − 5 products. key words: three-level network, logic minimization, adder, programmable logic IntroductionProgrammable logic arrays (PLAs) with two-input EXOR gates at the outputs, also known as AND-OR-EXOR PLAs ( Fig. 1) [28], are a powerful architecture to realize many logic functions. The AND-OR-EXOR PLA realizes an EXOR of two sum-of-products expressions (EX-SOP). Minimization of the number of products in EXSOPs is an important step in the optimization of AND-OR-EXOR PLAs, because the number of products is directly related to the cost of PLAs. EX-SOPs are promising because, for many practical logic functions, they often require many fewer products than sum-of-products expressions (SOPs) [7], [10], [11], [15], [16], [28].AND-OR-EXOR three-level networks are suitable for implementing adders, which serve as building blocks for synthesizing many other arithmetic circuits [21]. For example, Texas Instruments' SN181 arithmetic circuit and SN283 four-bit adder have two-input EXOR gates in the outputs [31]; Monolithic Memories' ZHAL20X8A eight-bit counter realizes EX-SOPs [19]. An AND-OR-EXOR is one of the simplest three-level architecture, since it contains only a single two-input EXOR gate. However, its logic capabil- ity is quite high. Because of this, various programmable logic devices (PLDs) with two-input EXOR gates in the outputs were developed. Important contributions of the paper are as follows:• We present a method to reduce the number of products in EX-SOPs by considering output phase optimization [26], where some components of the function are implemented in the complemented form.• We develop a heuristic method to minimize EX-SOPs for adders with two-and four-valued inputs by using an extension of the AOXMIN algorithm [10].• We proved that an n-bit adder with two-valued inputs requires at most 3·2 n−2 +7n−5 products in an EX-SOP.A crucial step in AOXMIN is to partition the products of an SOP of the given function into two sets, which is done by a random method. We propose a partitioning method for adders. Our experimental result demonstrates that, for an n-bit adder w...

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“…Among the many three-level forms described in the literature [2], [1], [5], [9], [10], [11], [13], [15], [17], we focus on three-level EXOR-AND-OR forms, introduced in [7], [8], [13]. These forms, also known as Sum of Pseudoproducts or SPP, are a direct generalization of AND-OR forms, obtained generalizing cubes to pseudocubes where literals in cubes may be replaced by EXOR factors in pseudocubes.…”

Section: Introductionmentioning

confidence: 99%

2-SPP Approximate Synthesis for Error Tolerant Applications

Bernasconi

Ciriani

2014

2014 17th Euromicro Conference on Digital System Design

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We propose an approximate logic synthesis heuristic for synthesizing a 2-SPP circuit under a given error rate threshold. 2-SPP circuits are three-level EXOR-AND-OR forms with EXOR gates restricted to fan-in 2. They represent a direct generalization of SOP forms, obtained generalizing cubes to "2-pseudocubes" where literals in cubes may be replaced by 2-EXOR factors in 2-pseudocubes. We discuss and experimentally evaluate two different measures for the error: the bit threshold and the minterm threshold. The first metric considers the overall number of complemented output bits, while the second metric is related to the number of input vectors on which the output computed by the circuit is different from the exact one on at least one bit. Experimental results confirm the effectiveness of the proposed approach. For an error rate threshold of 1%, our heuristic for approximate 2-SPP synthesis provides an average reduction of the number of 2-pseudocubes in the cover of about 23% for all the considered benchmarks, when we consider the bit threshold error metric. The reduction in the number of 2-pseudocubes is interesting even in the minterm threshold error metric, especially when we perform the resynthesis of the derived approximate versions of the benchmarks: the average gain, without resynthesis is of about 8%, while the average gain with resynthesis becomes 15%.

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A fast algorithm for or-and-or synthesis

Cited by 17 publications

References 25 publications

EXOR Projected Sum of Products

EXOR Projected Sum of Products

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders

2-SPP Approximate Synthesis for Error Tolerant Applications

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