A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions

There has been recent awareness of the drastic effects of interconnect delay in VLSI implementations, and several investigations focused on this problem have been linked directly to multiplier structures. The tree, or column compression techniques, used for partial product reduction have the severe impediment of highly irregular interconnections. A digital multiplier architecture will be presented in this paper that alleviates some of the problems associated with interconnect scaling, in addition to allowing for simple variable precision reconfiguration.Regulated by a 2-bit control signal, the multiplierprovides optimal circuitry for both single and double precision arithmetic, as well as fault tolerant and dual throughput single precision operation. Moreovel; dynamic power management techniques allow f o r 75% power reduction in single precision mode, and 50% power reduction for SlMD applications.

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Gigahertz-range MCML multiplier architectures

Srinivasan

Sulistyo

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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In this paper, we present three digital multiplier architectures capable of operating in the gigahertz range, based on MOS Current Mode Logic (MCML) style. A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, (3x2) counter (full adder), [4:2] compressor, and master-slave flip-flop were designed and optimized for high-speed operation. Using these gates, we propose three different 8-bit MCML binary-tree multiplier architectures and compare their performance in terms of latency, throughput (number of multiplications per second) and power consumption. According to our simulation, the fastest multiplier targeting for TSMC 0.18 µm CMOS technology attains a throughput of 4.76 GHz or 4.76 Billion multiplications per second and a latency of 3.8 ns.

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A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions

Cited by 3 publications

References 1 publication

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell

A reconfigurable digital multiplier architecture

Gigahertz-range MCML multiplier architectures

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