A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit

Ueno, Katsunori; Murakami, Hiroaki; Yano, N.; Okuda, Ryo; Himeno, T.; Kamei, T.; Urakawa, Y.

doi:10.1109/vlsic.2007.4342761

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…While there are prior reports of large synthesized blocks for processor designs, [15], [16], the LBSS core macros from POWER8 are designed to operate in excess of 4GHz with equivalent performance to custom implementations. POWER8 also contains many other LBSS macros spanning various sizes and design challenges; however the two LBSS units macros employ many design techniques described in previous sections of this paper and are ideal case studies of the LBSS methodology.…”

Section: Lbss Unit Level Design Examplesmentioning

confidence: 99%

POWER8 design methodology innovations for improving productivity and reducing power

Ziegler

Puri

Philhower

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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The design complexity of modern high performance processors calls for innovative design methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets.This paper describes new design approaches employed by the POWER8 processor design team to address complexity and power consumption challenges. Improvements in productivity are attained by leveraging a new and more synthesis-centric design methodology. New optimization strategies for synthesized macros allow power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor. Overall, POWER8 delivers a 2.5x increase in per-socket performance over its predecessor, POWER7+, while maintaining the same power dissipation.

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Section: Lbss Unit Level Design Examplesmentioning

confidence: 99%

POWER8 design methodology innovations for improving productivity and reducing power

Ziegler

Puri

Philhower

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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show abstract

“…Yet this is rarely done in practice because full-custom design at the transistor or gate level is simply too costly. Interestingly, recent work indicates that the gap between automated standard cell and custom design methodologies may be closing [6].…”

Section: Introductionmentioning

confidence: 99%

21st century digital design tools

Dally

Malachowsky

Keckler

2013

Proceedings of the 50th Annual Design Automation Conference

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Most chips today are designed with 20th century CAD tools. These tools, and the abstractions they are based on, were originally intended to handle designs of millions of gates or less. They are not up to the task of handling today's billion-gate designs. The result is months of delay and considerable labor from final RTL to tapeout. Surprises in timing closure, global congestion, and power consumption are common. Even taking an existing design to a new process node is a time-consuming and laborious process.Twenty-first century CAD tools should be based on higher-level abstractions to enable billion-gate chips to go from final RTL to tapeout in days, not months. Key to attaining this increase in productivity is raising the level of design and using simple, standard interfaces. Designs should be composed from high-level modules -processors, MODEMs, CODECs, memory subsystems, and I/O subsystems -rather than gates and flip-flops. Each module, which we expect to contain 100 thousand to 10 million gates, is easily laid out by today's tools, is placed as a unit, and communicates over a NoC via a standard interface. Restricting modules to standard sizes and aspect ratios further simplifies physical design. We expect even a large chip to contain at most a few thousand such modules and expect the physical design and chip-assembly to take a few days with minimal labor after completion of the module-level design.

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SpursEngine™ a high-performance stream processor derived from cell/B.E.™ for media processing acceleration

Hayashi

2008

2008 IEEE Hot Chips 20 Symposium (HCS)

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A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit

Cited by 5 publications

References 3 publications

POWER8 design methodology innovations for improving productivity and reducing power

POWER8 design methodology innovations for improving productivity and reducing power

21st century digital design tools

SpursEngine™ a high-performance stream processor derived from cell/B.E.™ for media processing acceleration

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