21st century digital design tools

Abstract

Most chips today are designed with 20th century CAD tools. These tools, and the abstractions they are based on, were originally intended to handle designs of millions of gates or less. They are not up to the task of handling today's billion-gate designs. The result is months of delay and considerable labor from final RTL to tapeout. Surprises in timing closure, global congestion, and power consumption are common. Even taking an existing design to a new process node is a time-consuming and laborious process.Twenty-first century CAD tools should be based on higher-level abstractions to enable billion-gate chips to go from final RTL to tapeout in days, not months. Key to attaining this increase in productivity is raising the level of design and using simple, standard interfaces. Designs should be composed from high-level modules -processors, MODEMs, CODECs, memory subsystems, and I/O subsystems -rather than gates and flip-flops. Each module, which we expect to contain 100 thousand to 10 million gates, is easily laid out by today's tools, is placed as a unit, and communicates over a NoC via a standard interface. Restricting modules to standard sizes and aspect ratios further simplifies physical design. We expect even a large chip to contain at most a few thousand such modules and expect the physical design and chip-assembly to take a few days with minimal labor after completion of the module-level design.

Effective Network Interface Architecture for Fault-Tolerant Mechanism Network-on-Chip

“…This process will suffer from some issues. Hence proposed system is introduced, this system will control the flow and full duplex communications [5].…”

Low power networks-on-Chip

“…A network structures the top-level wires simplifying their layout and giving them well-controlled electrical parameters. These well controlled electrical parameters in turn enable the use of high-performance circuits that result in significantly lower power dissipation and higher bandwidth that is possible with conventional circuits [25].…”

High-performance networks-on-chip

“…Figure 1.6 shows three different topologies used to connect 16 homogeneous tiled cores: (a) a ring, (b) a 2D Mesh and (c) a flattened butterfly. Since the NoC has to fit in the space left after the rest of the IPs are placed, the choice of the topology structure is primarily defined by the physical layout of the existing IP cores in the chip [59,28]. In homogeneous tiled CMPs, the regularity of the cores' layout allows the use of regular and homogeneous topologies, with minimal wiring overhead, such as rings and meshes.…”

“…In most systems, the NoC links can be routed only in intermediate metal layers with 2× and 4× lower resistance than the resistance of local routing layers. Metal layers reserved for local routing are used by the processing cores and their caches, while top metal layers (with almost 8× lower resistance) are primarily occupied by power and clock routing [120,28]. Therefore, the NoC links are accommodated within certain intermediate layers that are neither too resistive, nor too dense, thus allowing for low-delay link traversal.…”