A DC-to-1GHz tunable RF &amp;#x0394;&amp;#x03A3; ADC achieving DR &amp;#x003D; 74dB and BW &amp;#x003D; 150MHz at f&lt;inf&gt;0&lt;/inf&gt; &amp;#x003D; 450MHz using 550mW

Shibata, Hajime; Schreier, Richard; Yang, Wenhua; Shaikh, Ali; Paterson, Donald; Caldwell, Trevor; Alldred, David; Lai, Ping Wing

doi:10.1109/isscc.2012.6176954

Cited by 18 publications

(13 citation statements)

References 5 publications

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“…This section analyses two of the most critical limitations in LC-based BP CT-Σ∆Ms, namely: finite quality factor of integrated inductors and circuit-element tolerances 2 . 2 Other error mechanisms such as jitter and thermal noise, may also degrade the performance of the modulators under study. However, their effect -beyond the scope of this paper -is mainly contributed by the circuits at the modulator front-end, thus affecting in a similar way to the BP CT-Σ∆Ms under study.…”

Section: Effect Of Circuit Errorsmentioning

confidence: 99%

On the use of passive circuits to implement LC-based band-pass CT ΣΔ modulators

Salgado

Dolecek

Rosa

2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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This paper discusses the use of passive circuits for the implementation of band-pass continuous-time Σ∆ modulators intended for digitizing radio-frequency signals in wireless communication systems. Several alternative loop filters, considering either a fully passive or an hybrid active/passive circuit realization of the embedded resonators, are applied to the highlevel design of fourth-order single-loop band-pass Σ∆ modulators with current-mode feedback digital-to-analog converter. The resulted modulator topologies are synthesized considering a widely programmable notch frequency, and compared in terms of their sensitivity to main circuit error mechanisms, including finite output swing, quality factor of inductors, and technology process variations. Time-domain simulations validate the presented approach, showing the feasibility of using fully passive and hybrid active/passive resonators to implement bandpass continuous-time Σ∆ analog-to-digital converters 1 .

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Section: Effect Of Circuit Errorsmentioning

confidence: 99%

On the use of passive circuits to implement LC-based band-pass CT ΣΔ modulators

Salgado

Dolecek

Rosa

2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…This flexibility can be reached at the cost of a tunable RF bandpass loop filter. For instance, [65] demonstrates a tunable 6 th -order feedback RF ΔΣ ADC with DR=74 dB and BW=150 MHz, using a combination of one RC and two LC resonators to cover the DC-to-1 GHz RF input band. The converter necessitates the use of two external inductances, and exhibit large performance variations across the RF band due to the switching between the three filters.…”

Section: Direct Rf Digitization Receivermentioning

confidence: 99%

Broadband Direct RF Digitization Receivers

Jamin¹

2014

Analog Circuits and Signal Processing

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“…Such an RF ADC should be tunable over several GHz, have programmable gain, low noise, be blocker-tolerant, and consume minimal power. As an attempt to satisfy these requirements, delta-sigma (ΔΣ) modulation close to the antenna interface has been proposed in both bandpass [1], [2] and downconverting [3], [4] configurations. The latter technique enables simpler GHz-range wideband (WB) operation with low power consumption, but such receivers navigate a tradeoff between sensitivity and blocker toleration.…”

mentioning

confidence: 99%

28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS

Englund

Ostman

Viitala

et al. 2014

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

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The software-defined radio paradigm calls for increasingly digital-intensive programmable receivers, ideally placing the analog-to-digital converter (ADC) right at the antenna. Such an RF ADC should be tunable over several GHz, have programmable gain, low noise, be blocker-tolerant, and consume minimal power. As an attempt to satisfy these requirements, delta-sigma (ΔΣ) modulation close to the antenna interface has been proposed in both bandpass [1], [2] and downconverting [3], [4] configurations. The latter technique enables simpler GHz-range wideband (WB) operation with low power consumption, but such receivers navigate a tradeoff between sensitivity and blocker toleration. The narrowband (NB) direct ΔΣ structure introduced in [3] combined RF N-path filtering, upconverted ΔΣ RF feedback, and a second RF gain stage to obtain acceptable noise and linearity simultaneously. In this paper we present a WB direct ΔΣ receiver, designed for programmable, inductorless operation in the long-term evolution (LTE) frequency division duplexing bands from 0.7 to 2.7GHz. The 40nm CMOS circuit uses a supply of 1.1V and provides RF channel bandwidths up to 20MHz, 37dB maximum gain, NF of 5.9 to 8.8dB, and -2dBm IIP3. A design strategy that emphasizes ΔΣ coefficient programmability ensures good performance throughout the frequency range.The wideband direct ΔΣ receiver structure embeds a direct-conversion RF front-end into a ΔΣ ADC. Channel filtering, signal downconversion, and quantization noise shaping are thus performed simultaneously, with the filtering characteristic being emphasized in wideband employment. The continuous-time 4-stage feedback modulator architecture depicted in Fig. 28.1.1 was selected as a good tradeoff between complexity, stability, and sufficient blocker filtering. The loop filter baseband bandwidth f BW can be programmed to 1 or 10 MHz. In contrast to conventional ΔΣ modulators, the receiver emphasizes blocker filtering in the signal transfer function (STF) at the cost of SNDR when the channel bandwidth approaches f BW . To minimize SNDR reduction, the internal feedback coefficient g 2 is used to create an NTF notch, which enhances noise shaping close to the band edge. The coefficients b 1 and a 2 can be adjusted to lower the gain of the receiver by a maximum of 15dB, while preserving the shape of the STF. A half clock cycle delayed feedback to the input of the quantizer (b ELDC ) is used to compensate for the delay in the feedback path.In the RF section, the first ΔΣ integrator stage consists of a common-source LNA with adjustable active common-drain RC feedback, loaded by PMOS devices and an N-path filter, as shown in Fig. 28.1.2. This combination sets the ΔΣ coefficients a 1 and g 1 , and the center frequency of the N-path filter controls the S 11 notch of the receiver. Moreover, the combination simultaneously creates an inductorless blocker-filtering RF resonator and an RF integrator response at the LNA output node, with the center frequency of both being controlled by f LO . At the highest operating f...

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A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f<inf>0</inf> = 450MHz using 550mW

Cited by 18 publications

References 5 publications

On the use of passive circuits to implement LC-based band-pass CT ΣΔ modulators

On the use of passive circuits to implement LC-based band-pass CT ΣΔ modulators

Broadband Direct RF Digitization Receivers

28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS

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A DC-to-1GHz tunable RF &#x0394;&#x03A3; ADC achieving DR &#x003D; 74dB and BW &#x003D; 150MHz at f<inf>0</inf> &#x003D; 450MHz using 550mW

Cited by 18 publications

References 5 publications

On the use of passive circuits to implement LC-based band-pass CT &#x03A3;&#x0394; modulators

On the use of passive circuits to implement LC-based band-pass CT &#x03A3;&#x0394; modulators

Broadband Direct RF Digitization Receivers

28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS

Contact Info

Product

Resources

About

A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f<inf>0</inf> = 450MHz using 550mW

On the use of passive circuits to implement LC-based band-pass CT ΣΔ modulators

On the use of passive circuits to implement LC-based band-pass CT ΣΔ modulators