28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS

N-path techniques have become a popular candidate alternative to external pre-selection filtering in wireless receivers. Their main attraction lies in enabling tunable on-chip high-filters, with straightforward migration from one CMOS node to another. However, parasitic capacitance at the N-path filter input offsets the bandpass response from the desired center frequency in wideband circuits. In this paper, we focus on an LNA-first receiver and show that the offset at the LNA output varies in magnitude depending on LNA and filter load impedance properties. An offset-tuning approach is then evaluated for its effects on receiver gain and noise and to obtain design guidelines. We propose a digitally controllable implementation that preserves front-end gain and linearity, with a small penalty on receiver NF. A programmable 0.7-2.7-GHz front-end in 40-nm CMOS verifies the functionality. At 1.7 GHz, the front-end has a gain of 37 dB, a NF of 5.2 dB, and an out-of-band IIP3 of 1 dBm. Mikko Kaltiokallio (S'07-M'13) received the M.Sc. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 2006. In 2014 he received the D.Sc. degree in the same field at Aalto University, Espoo, Finland. From 2005 to 2013, he was with the Electronic Circuit Design Laboratory, Helsinki University of Technology and later Aalto University. Since 2013, he has been with the Nokia Corp. working with front-end circuits. His research interests lie in the wideband high-linearity radio front-ends, mixed-signal RF and baseband design, and quadrature and LO buffering circuits. Kari Stadius (S'95-M'03) received the M.Sc., Lic. Tech., and D.Sc. degrees in electrical engineering from the Helsinki University of Technology, Helsinki, Finland, in 1994, 1997 He is currently working as a staff scientist at the Department of Micro-and Nanosciences, Aalto University School of Electrical Engineering, Finland. His research interests include CMOS RF circuits for communications with special emphasis on frequency synthesis, analog and mixed-mode circuit design, and new emerging RF technologies such as graphene. He has authored or coauthored over 70 refereed journal and conference papers in the areas of analog and RF circuit design.Kimmo Koli (M'95) was born in Karuna, Finland, in 1964. He received his M.Sc., Licentiate in Technology, and D.Sc. degrees in electrical on audio and sensor interfaces and wireless tranceivers. From 2008 to 2013, he joined STMicroelectronics (later ST-NXP Wireless and ST-Ericsson) and is currently with Ericsson, Turku, Finland, focusing on RF design blocks for wireless applications.Dr. Koli has authored or coauthored over 40 journal articles and conference papers and holds several patents. He has served for several years as a member of the technical program committee of IEEE International Solid-State Circuits

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“…12 shows a micrograph of the RF blocks of the front-end. It was designed in conjunction with [17], with the pertinent active area being 0. 5 .…”

Section: Resultsmentioning

confidence: 99%

Analysis and Design of N-Path Filter Offset Tuning in a 0.7–2.7-GHz Receiver Front-End

Ostman

Englund

Viitala

et al. 2015

IEEE Trans. Circuits Syst. I

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“…A digital-intensive RF receiver can be classified into three different types: RF sampling, Sub-sampling, and Delta-Sigma Modulator (DSM). Among the stateof-the-art DSM-based architectures, the direct Delta-Sigma receiver (DDSR) combining the analog frontend and Delta-Sigma Analog-to-Digital Converter (ADC), is considered as the most suitable candidate for wireless applications [1,2,3,4]. This architecture offers promising advantages such as high resolution, high dynamic range, and low complexity.…”

Section: Introductionmentioning

confidence: 99%

A Configurable Direct Delta-Sigma Converter for Frequency Division Duplex (FDD) Bands from 0.4 GHz to 3.6 GHz

2022

JST: SSAD

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This paper presents a novel design of 5th order direct delta-sigma receiver for multi-band multi-standard wireless applications. The receiver is designed to cover Frequency Division Duplex (FDD) bands from 0.4 GHz to 3.6 GHz with a configurable bandwidth of 3.84 MHz (WCDMA), and 9.0/13.5/18/37 MHz (LTE-10M/15M/20M/37M) complying with 3GPP specifications. The configuration is implemented and controlled by a digital controller. System modelling in MATLAB is carried out to tune the key design parameters aiming to optimize noise figure (NF) and linearity of the receiver. The post-simulation results of the receiver show a good match with that of the MATLAB receiver model, an NF of 2.5 dB, an in-band (IB) third-order intercept point (IIP3) of −15 dBm, an out-of-band (OOB) IIP3 of 0 dBm, and a peak signal-to-noise-and-distortion ratio (SNDR) of 58 dB. The receiver is designed in 65-nm CMOS technology with a 70-mA static current and a 1.2-V voltage supply.

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“…The CT type uses a resistor-capacitor (RC) integrator, which allows continuous operation and high-speed processing. The CT-type modulator is therefore often used in communication applications [1]. Commonly, the RC integrator uses a first-order, low-pass filter as an anti-aliasing filter.…”

Section: Introductionmentioning

confidence: 99%

Delta-Sigma ADC Based on Switched-Capacitor Integrator with FIR Filter Structure

Saikatsu

Yasuda

2019

IEICE Trans. Fundamentals

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This paper presents a novel delta-sigma modulator that uses a switched-capacitor (SC) integrator with the structure of a finite impulse response (FIR) filter in a loop filter configuration. The delta-sigma analog-to-digital converter (∆ΣADC) is used in various conversion systems to enable low-power, high-accuracy conversion using oversampling and noise shaping. Increasing the gain coefficient of the integrator in the loop filter configuration of the ∆ΣADC suppresses the quantization noise that occurs in the signal band. However, there is a trade-off relationship between the integrator gain coefficient and system stability. The SC integrator, which contains an FIR filter, can suppress quantization noise in the signal band without requiring an additional operational amplifier. Additionally, it can realize a higher signal-to-quantization noise ratio. In addition, the poles that are added by the FIR filter structure can improve the system's stability. It is also possible to improve the flexibility of the pole placement in the system. Therefore, a noise transfer function that does not contain a large gain peak is realized. This results in a stable system operation. This paper presents the essential design aspects of a ∆ΣADC with an FIR filter. Two types of simulation results are examined for the proposed first-and second-order, and these results confirm the effectiveness of the proposed architecture.

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28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS

Cited by 4 publications

References 6 publications

Analysis and Design of N-Path Filter Offset Tuning in a 0.7–2.7-GHz Receiver Front-End

Analysis and Design of N-Path Filter Offset Tuning in a 0.7–2.7-GHz Receiver Front-End

A Configurable Direct Delta-Sigma Converter for Frequency Division Duplex (FDD) Bands from 0.4 GHz to 3.6 GHz

Delta-Sigma ADC Based on Switched-Capacitor Integrator with FIR Filter Structure

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