No abstract

N-path techniques have become a popular candidate alternative to external pre-selection filtering in wireless receivers. Their main attraction lies in enabling tunable on-chip high-filters, with straightforward migration from one CMOS node to another. However, parasitic capacitance at the N-path filter input offsets the bandpass response from the desired center frequency in wideband circuits. In this paper, we focus on an LNA-first receiver and show that the offset at the LNA output varies in magnitude depending on LNA and filter load impedance properties. An offset-tuning approach is then evaluated for its effects on receiver gain and noise and to obtain design guidelines. We propose a digitally controllable implementation that preserves front-end gain and linearity, with a small penalty on receiver NF. A programmable 0.7-2.7-GHz front-end in 40-nm CMOS verifies the functionality. At 1.7 GHz, the front-end has a gain of 37 dB, a NF of 5.2 dB, and an out-of-band IIP3 of 1 dBm. Mikko Kaltiokallio (S'07-M'13) received the M.Sc. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 2006. In 2014 he received the D.Sc. degree in the same field at Aalto University, Espoo, Finland. From 2005 to 2013, he was with the Electronic Circuit Design Laboratory, Helsinki University of Technology and later Aalto University. Since 2013, he has been with the Nokia Corp. working with front-end circuits. His research interests lie in the wideband high-linearity radio front-ends, mixed-signal RF and baseband design, and quadrature and LO buffering circuits. Kari Stadius (S'95-M'03) received the M.Sc., Lic. Tech., and D.Sc. degrees in electrical engineering from the Helsinki University of Technology, Helsinki, Finland, in 1994, 1997 He is currently working as a staff scientist at the Department of Micro-and Nanosciences, Aalto University School of Electrical Engineering, Finland. His research interests include CMOS RF circuits for communications with special emphasis on frequency synthesis, analog and mixed-mode circuit design, and new emerging RF technologies such as graphene. He has authored or coauthored over 70 refereed journal and conference papers in the areas of analog and RF circuit design.Kimmo Koli (M'95) was born in Karuna, Finland, in 1964. He received his M.Sc., Licentiate in Technology, and D.Sc. degrees in electrical on audio and sensor interfaces and wireless tranceivers. From 2008 to 2013, he joined STMicroelectronics (later ST-NXP Wireless and ST-Ericsson) and is currently with Ericsson, Turku, Finland, focusing on RF design blocks for wireless applications.Dr. Koli has authored or coauthored over 40 journal articles and conference papers and holds several patents. He has served for several years as a member of the technical program committee of IEEE International Solid-State Circuits

No abstract

The software-defined radio paradigm calls for increasingly digital-intensive programmable receivers, ideally placing the analog-to-digital converter (ADC) right at the antenna. Such an RF ADC should be tunable over several GHz, have programmable gain, low noise, be blocker-tolerant, and consume minimal power. As an attempt to satisfy these requirements, delta-sigma (ΔΣ) modulation close to the antenna interface has been proposed in both bandpass [1], [2] and downconverting [3], [4] configurations. The latter technique enables simpler GHz-range wideband (WB) operation with low power consumption, but such receivers navigate a tradeoff between sensitivity and blocker toleration. The narrowband (NB) direct ΔΣ structure introduced in [3] combined RF N-path filtering, upconverted ΔΣ RF feedback, and a second RF gain stage to obtain acceptable noise and linearity simultaneously. In this paper we present a WB direct ΔΣ receiver, designed for programmable, inductorless operation in the long-term evolution (LTE) frequency division duplexing bands from 0.7 to 2.7GHz. The 40nm CMOS circuit uses a supply of 1.1V and provides RF channel bandwidths up to 20MHz, 37dB maximum gain, NF of 5.9 to 8.8dB, and -2dBm IIP3. A design strategy that emphasizes ΔΣ coefficient programmability ensures good performance throughout the frequency range.The wideband direct ΔΣ receiver structure embeds a direct-conversion RF front-end into a ΔΣ ADC. Channel filtering, signal downconversion, and quantization noise shaping are thus performed simultaneously, with the filtering characteristic being emphasized in wideband employment. The continuous-time 4-stage feedback modulator architecture depicted in Fig. 28.1.1 was selected as a good tradeoff between complexity, stability, and sufficient blocker filtering. The loop filter baseband bandwidth f BW can be programmed to 1 or 10 MHz. In contrast to conventional ΔΣ modulators, the receiver emphasizes blocker filtering in the signal transfer function (STF) at the cost of SNDR when the channel bandwidth approaches f BW . To minimize SNDR reduction, the internal feedback coefficient g 2 is used to create an NTF notch, which enhances noise shaping close to the band edge. The coefficients b 1 and a 2 can be adjusted to lower the gain of the receiver by a maximum of 15dB, while preserving the shape of the STF. A half clock cycle delayed feedback to the input of the quantizer (b ELDC ) is used to compensate for the delay in the feedback path.In the RF section, the first ΔΣ integrator stage consists of a common-source LNA with adjustable active common-drain RC feedback, loaded by PMOS devices and an N-path filter, as shown in Fig. 28.1.2. This combination sets the ΔΣ coefficients a 1 and g 1 , and the center frequency of the N-path filter controls the S 11 notch of the receiver. Moreover, the combination simultaneously creates an inductorless blocker-filtering RF resonator and an RF integrator response at the LNA output node, with the center frequency of both being controlled by f LO . At the highest operating f...

No abstract