Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II-III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV-VI). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter.
Dynamic performance of high speed, high resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization and clock jitter are all culprits. A DAC output current controlled by an oscillating waveform is proposed to mitigate the effects of the switching distortion. The oscillating waveform should be a multiple (k*fs) of the sampling frequency (fs), where k>1. The waveforms can be aligned so that the data switching occurs in the zero regions of the oscillating output. This makes the DAC insensitive to switch dynamics and jitter. The architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency. An image of a low IF input signal can therefore be output directly at a high IF or RF frequency for transmit communications applications. A narrowband sigma-delta DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept. A sigma-delta architecture allows the current source transistors to be smaller since mismatch shaping is employed. Smaller current source transistors have a lower drain capacitance, allowing large high frequency output impedance to be achieved without an extra cascode transistor. Elimination of the cascode reduces transistor headroom requirements and allows the DAC to be built with a 1.8V supply. The RF DAC prototype is targeted to GSM transmit specifications and implemented in 0.1 8ptm CMOS technology. Measured single-tone SFDR is -75dBc, SNR is 52dB, and IMD3 is -70.8dBc over a 17.5MHz bandwidth centered at 942.5MHz. Measured SNR has the predicted dependence on the phase alignment of the data clock and oscillating pulse.
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