A cycle-level SIMT-GPU simulation framework

Wang, Po-Han; Lo, Chien-Wei; Yang, Chia-Lin; Cheng, Yu-Jung

doi:10.1109/ispass.2012.6189213

Cited by 7 publications

(2 citation statements)

References 2 publications

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“…This simulator models the integrated CPU/GPU architecture with shared LLC in a cycle-level manner. It integrates a GPU model (SIMT-GPU [19] for graphics applications and GPGPU-Sim 3.2.1 [2] for GPGPU applications) with MARSSx86 [13]. DRAMSim2 [16] is also integrated to provide detailed timing for memory accesses.…”

Section: Evaluation Methodologymentioning

confidence: 99%

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Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture

Wang

Yang

2016

Proceedings of the 53rd Annual Design Automation Conference

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Shared last-level cache (LLC) management is a critical design issue for heterogeneous multi-cores. In this paper, we observe two major challenges: the contribution of LLC latency to overall performance varies among applications/cores and also across time; overlooking the off-chip latency factor often leads to adverse effects on overall performance. Hence, we propose a Latency Sensitivity-based Cache Partitioning (LSP) framework, including a lightweight runtime mechanism to quantify the latency-sensitivity and a new cost function to guide the LLC partitioning. Results show that LSP improves the overall throughput by 8% on average (27% at most), compared with the state-of-the-art partitioning mechanism, TAP.

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Section: Evaluation Methodologymentioning

confidence: 99%

“…Table 2: Configurations of the evaluated heterogeneous system. All of the CPU benchmarks are taken from SPEC2006, and the GPU benchmarks are taken from various sources, including NVIDIA CUDA SDK, Rodinia [4], OpenGL ES kernels [19], and open source applications [11]. The cache warm-up phase of the benchmarks are excluded.…”

Section: Evaluation Methodologymentioning

confidence: 99%