A cost-driven lithographic correction methodology based on off-the-shelf sizing tools

Abstract

As minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requirement for dimensional variation control, especially in critical dimension (CD) 3σ, has become more stringent. To meet these requirements, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase shift mask (PSM) technology are applied. These approaches result in a substantial increase in mask costs and make the cost of ownership (COO) a key parameter in the comparison of lithography technologies. No concept of function is injected into the mask flow; that is, current OPC techniques are oblivious to the design intent, and the entire layout is corrected uniformly with the same effort. We propose a novel minimum cost of correction (MinCorr) methodology to determine the level of correction for each layout feature such that prescribed parametric yield is attained with minimum total RET cost. We highlight potential solutions to the MinCorr problem and give a simple mapping to traditional performance optimization. We conclude with experimental results showing that substantial RET costs may be saved while maintaining a given desired level of parametric yield.

Design-Aware Mask Inspection

“…In order to estimate the delay change caused by this defect, the transistor is sliced into three parts as shown in Fig. 6 (similar to [24]) to estimate the effective W L as shown in (1). Using first-order transistor models, we can then estimate 5 For simplicity and pessimism, we use minimum DR rules instead of using exact design values.…”

“…The increasing aggressiveness of various resolution-enhancement techniques such as optical proximity correction (OPC), phase shift mask, and subresolution assist features (SRAFs) along with decreasing feature sizes has increased the complexity, and therefore the cost, of reticles considerably [1]. Keeping mask cost in control is extremely critical, especially for lowvolume designs.…”

Analytical thermal placement for VLSI lifetime improvement and minimum performance variation

“…continually afford opportunities to leverage design information for cost and turnaround time improvements. For example, in a regime of rising mask costs, design-aware modulation of mask complexity [23], or design-aware inspection and defect disposition, could respectively reduce mask write times or increase tolerances for functionally insignificant features. As another example, ASML's Dose Mapper technology has been extensively used within the automatic process control context to improve global CD uniformity.…”

A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology

“…With respect to the cost breakdown shown in Figure 1, OPC affects mask data preparation (MDP), defect inspection (and implicitly defect repair), and the mask-writing process itself. Today, variable-shaped electron beam mask writers, in combination with vector scanning 1 , comprise the dominant approach to highspeed mask writing. In the standard mask data preparation flow, the input GDSII layout data is converted into the mask writer format by fracturing into rectangles or trapezoids of different dimensions.…”

“…Traditionally the mask flow has suffered from a lack of design information, such that all features (whether critical or non-critical) are treated alike by RET insertion. A recent work [1] proposes to exploit design information (timing slacks) to reduce OPC data volume, but has a number of impractical aspects. In this paper, we propose an implementable flow that drives model-based OPC explicitly by timing constraints, with the objective of reducing mask data volume and OPC runtime.…”