A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology

Abstract

With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RETs) such as optical proximity correction (OPC) are an integral part of the design to mask flow. OPC adds complex features to the layout, resulting in mask data volume explosion and increased mask costs. Traditionally the mask flow has suffered from a lack of design information, such that all features (whether critical or non-critical) are treated alike by RET insertion. A recent work [1] proposes to exploit design information (timing slacks) to reduce OPC data volume, but has a number of impractical aspects. In this paper, we propose an implementable flow that drives model-based OPC explicitly by timing constraints, with the objective of reducing mask data volume and OPC runtime. We apply a mathematical programming based slack budgeting algorithm to determine edge placement error (EPE) tolerance budgets for all polysilicon gate geometries. These tolerances are then enforced by a commercial OPC tool to achieve up to 24% MEBES data volume and 41% OPC runtime reductions on a suite of six testcases implemented in Artisan TSMC 0.13um libraries.

Voltage-Island Partitioning and Floorplanning Under Timing Constraints

“…Although the work of Gupta et al focuses on dual-thresholdvoltage assignment (i.e., the work deals with more than the assignment problem for the comparative study here), it is still significant to make the comparison with its core technique since the work of Gupta et al is a state-of-the-art method for voltage assignment. The equation presented in [11] and employed for the comparative study is given as follows:…”

“…Take the same illustration shown in Lemma 1 for example. Each resulting point in the final DP curve of b f is generated [11] from J m 's and J n 's points, which are recursively generated from b m 's and b n 's fan-ins with the minimum power; as a result, (13) again and again requests for the points with the minimum power. It is obvious that the voltage-assignment algorithm has overlapping subproblems.…”

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

“…Sensitivity-based downsizing approaches have been proposed in [10], [24], [25], [15], [13], and [14]. TILOS [10] proposes a heuristic that sizes transistors iteratively, according to the sensitivity of the critical path delay to the transistor sizes, in order to find an optimum (with maximum delay reduction / transistor width increase).…”

“…The techniques proposed in [13] and [14] use sensitivity-based downsizing (i.e., begin with all nominal cell variants and replace cells on non-critical paths with long channel-length variants) heuristics for leakage optimization.…”

“…The sensitivities are computed for all cell instances. The heuristics of [13], [14] select a cell with the largest sensitivity and perform downsizing with a logically equivalent cell. If there is no timing violation in incremental STA, this move is accepted and saved.…”