Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

Abstract

Conventional CAD methodologies optimize a processor module for correct operation and prohibit timing violations during nominal operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of correct operation. The target error rate is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. We show that significant power benefits are possible from a recovery-driven design approach that deliberately allows errors caused by voltage overscaling to occur during nominal operation, while relying on an error resilience technique to tolerate these errors. We present a detailed evaluation and analysis of such a design-level methodology that minimizes the power of a processor module for a target error rate. We show how this design-level methodology can be extended to design recovery-driven processors -processors that are optimized to take advantage of hardware or software error resilience. These may be single-core processors or heterogeneously-reliable multi-core processors, in which individual cores are optimized for different reliability targets. We also discuss a gradual slack recovery-driven design approach that optimizes for a range of error rates to create soft processors -processors that have graceful failure characteristics and the ability to trade throughput or output quality for additional energy savings over a range of error rates. We demonstrate significant power benefits over conventional design -11.8% on average over all modules and error rate targets, and up to 29.1% for individual modules. Processorlevel benefits are 19.0%, on average. Benefits increase when recovery-driven design is coupled with an error resilience mechanism or when the number of available voltage domains increases.ii ACKNOWLEDGMENTS

Software canaries

“…For the remaining 3.6% of the potentially-critical timing paths, we have the option of using Razor II [5] as a canary circuit to provide coverage. Razor II is modeled following the methodology described in [15]. (Note that Razor II [5] is different than Razor-based timing speculation [8] and can be used as a canary circuit.)…”

“…Fine-grained hardware-based BTWC mechanisms (e.g., timing speculation [5,1]) can test for timing slack on the critical paths of a processor but have considerable static and dynamic overhead when all potentially-critical paths are targeted (e.g., 25% [15] to 87% [9]), especially in the context of microprocessors where a large fraction of timing paths are potentially-critical [23,14]. Note that it is possible to use timing speculation and SPDFT synergistically to maximize system efficiency (see Section 3.6).…”

Lithography-induced limits to scaling of design quality

“…Recoverydriven design is a design approach that optimizes a processor module for a target timing error rate instead of correct operation. 21 The target error rate is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. .…”

Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors

“…For example, [14] have shown up to 13% standard-cell area reduction from a 40% model guardband reduction. In [15], the authors pair a better-than-worst-case design core with recovery-driven techniques and report power savings in the range of 11.8% to 29.1%. We will focus on exploiting such heterogeneity in platforms consisting of two cores featuring the same architecture, but two different implementation methodologies: one designed reliably using worst-case (Heavy) design margins, and another designed using more energy-efficient, typical (Light) design margins.…”