“…STI stress results in a strained region in the active area, thus affecting the silicon bandgap, the diffusivity of impurities in silicon, and the mobility of both electrons and holes. [13] As the device scales in the width direction, the impact of STI stress becomes severe on the electrical parameter of the parasitic corner transistors, such as threshold voltage, saturation drain current, and off-state leakage current. For narrow devices where the STI spacing is smaller, there is more compressive stress, which may increase the doping concentration at the STI sidewall, increasing the threshold voltage of the parasitic back corner transistor.…”