A compact, low power, fully integrated clock frequency doubler

Tajalli, Armin; Khodaverdi, A.; Atarodi, M.

doi:10.1109/icecs.2003.1301847

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Cited by 3 publications

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“…It can be constructed utilizing PLL, DLL with RS flip-flops [1] or other units with XOR gates [2,3,4] and [5]. A tunable charge pump and feedback scheme has been used in [3].…”

Section: Introductionmentioning

confidence: 99%

Fully digital clock frequency doubler

Jung

Park²,

Cho

et al. 2010

IEICE Electron. Express

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This paper presents a clock frequency doubler, having the function of automatic adjustable duty cycle without feedback loops. The duty cycle amount can be automatically adjustable using digitized delay block and a counter. This simplifies the design structure and allows the circuit to operate over a wide range of input frequency variation. The simulation results show that this frequency doubler operates at a very wide variable input frequency ranging from 650 MHz to 1.25 GHz.

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“…It can be constructed utilizing PLL, DLL with RS flip-flops [1] or other units with XOR gates [2,3,4] and [5]. A tunable charge pump and feedback scheme has been used in [3].…”

Section: Introductionmentioning

confidence: 99%