Fully digital clock frequency doubler

Abstract

This paper presents a clock frequency doubler, having the function of automatic adjustable duty cycle without feedback loops. The duty cycle amount can be automatically adjustable using digitized delay block and a counter. This simplifies the design structure and allows the circuit to operate over a wide range of input frequency variation. The simulation results show that this frequency doubler operates at a very wide variable input frequency ranging from 650 MHz to 1.25 GHz.

Fully digital synchronous frequency doubler for FM stereo decoder

“…The multipliers are implemented using shifters and adders. For this, the filter coefficients are converted to powers of two using CSD algorithm [6]. In figure 4, there are two filters; Filter-I and Filter-Q.…”

“…For doubling the pilot tone, phase Locked Loops (PLLs) or Delay Locked Loops (DLLs) are used for better noise performance. However, the designs based on PLL/DLL are complex comprising phase detector, up-down counter, oscillator and other control circuits [4][5][6][7]. Instead of using complex PLLs or asynchronous delay element in the design of FM stereo decoder, phase shifter based frequency doublers can be used.…”