Clock frequency doubler circuit for multiple frequencies and its application in a CDN to reduce power

Reuben, John; Anuroop, Abishek; Kittur, Harish M.

doi:10.1109/icceet.2012.6203744

Cited by 3 publications

(2 citation statements)

References 7 publications

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“…Clock doublers have become increasingly prevalent in integrated circuits. In use, they can be incorporated at the input of a phase-locked loop (PLL) and utilized with UARTs to achieve greater bandwidth, while also serving as a valuable component in a clock distribution network [1,2]. To achieve this, on-chip clock multiplication has become essential.…”

Section: Introductionmentioning

confidence: 99%

Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process

Kim

Lee

2023

Electronics

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In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock and the frequency of various applications through an edge combiner (EC). A simpler structure is more sensitive to process, voltage, and temperature (PVT), so DLL complements itself quickly in the feedback system and improves the stability of the final output. The proposed DLL-based multiplier can prevent harmonic lock generation using a first phase canceller (FPC), thus compensating for faster lock time. The circuit is built with a 55 nm CMOS process and has a chip area of 0.0225 mm2. The proposed design achieves a total power consumption of 0.48 mW at the 30.72 MHz operating clock frequency, and the clock duty can also operate stably from 15 to 75%.

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Section: Introductionmentioning

confidence: 99%

Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process

Kim

Lee

2023

Electronics

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“…However, these networks dissipate higher power [9]. To reduce power dissipation of grid and meshes network, researcher [11] has recommended a reduced voltage swing methodology and researcher [12] has recommended the use of clock frequency multiplier circuitry. Both methods caused an increase in the complexity of analysis and consequently adding risk to the design yield.…”

Section: Introductionmentioning

confidence: 99%

Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique

et al. 2021

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This paper recommends a practical technique to design full chip (FC) clock tree of a complex system-on-chip (SoC). In the new business environment, the market prefers a highly integrated but low power SoC with fast design productivity and low development cost. We observed that many techniques proposed in the prior arts are no longer practical or enough. With that, we introduce a flexible FC Clock network topology and a synthesis algorithm that utilize a hybrid meta-heuristic technique to search for near optimum solution in shorter turn-around time. Our work on a 10nm SoC product showed that the topology and algorithm managed to produce averagely 16.98% better global skew, 42.75% less divergence on critical clock paths and with 64.5% shorter clock balancing phase compared to a conventional ASIC methodology.INDEX TERMS system-on-a-chip (SoC), clock distribution, deep sub-micrometer, artificial intelligence, hybrid meta-heuristic.

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