Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique

Abstract

This paper recommends a practical technique to design full chip (FC) clock tree of a complex system-on-chip (SoC). In the new business environment, the market prefers a highly integrated but low power SoC with fast design productivity and low development cost. We observed that many techniques proposed in the prior arts are no longer practical or enough. With that, we introduce a flexible FC Clock network topology and a synthesis algorithm that utilize a hybrid meta-heuristic technique to search for near optimum solution in shorter turn-around time. Our work on a 10nm SoC product showed that the topology and algorithm managed to produce averagely 16.98% better global skew, 42.75% less divergence on critical clock paths and with 64.5% shorter clock balancing phase compared to a conventional ASIC methodology.INDEX TERMS system-on-a-chip (SoC), clock distribution, deep sub-micrometer, artificial intelligence, hybrid meta-heuristic.

Comprehensive Review of Optimal Utilization of Clock and Power Resources in Multi Bit Flip Flop Techniques

“…During physical synthesis, authors have tried and succeeded in developing the physical design flow for MBFFs. The developed works are divided into three different categories: 1) MBFFs pre-placement optimization (25) , 2) In-placement register banks optimization (26) , 3) MBFFs post-placement optimization (27) .…”

“…Instead of following the heuristic criteria to generate register banks in large size and disassembling the banks for incremental placement in recent works (30) , it's better to adopt different problem formulation in the post-placement stage to generate MBFFs with the satisfaction of placement and timing constraints. N/A The total minimum power of the flip-flop (25) Maximum rout ability The total minimum power of the flip-flop [27] Minimum total wire length The total minimum power of the flip-flop and wire length (27) Minimum total net switching power Net switching power and total minimum number of clock sinks (28) Minimum total wire length Total minimum flip-flop power…”