A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

Abstract

We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads.

A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors

“…Lumped components such as inductors and capacitors are widely adopted in RF circuits based on CMOS technologies [16,17]. A great deal of efforts has been made by researchers to get an accurate model of lumped inductors and metal-insulator-metal (MIM) capacitors for the implementation in RF circuits [18,19].…”

A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology

“…Instead of switch mode, the proposed PA works in linear mode. This ensures the proposed PA can support any modulation scheme without limitations [28]. The proposed PA is implemented with a transformer-based matching network (TMN) to provide more degrees of design freedom, while occupying similar chip area as a single inductor [29].…”