A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniques

Le-Thai, Ha; Xhakoni, Adi; Gielen, Georges

doi:10.1109/esscirc.2016.7598282

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…In combination with the second-order topology, the conversion time improves, resulting in high A pixel /(A ADC T * ADC ). Second-order I ADCs are also used in [41] and [42] in which the latter dynamically reduces the quantization step by choosing a smaller V ref for low-light signals (since the quantization noise is more dominant at low-light levels). This results in less cycles and a 2.75 times improvement of T * ADC with a small overhead due to the additional comparator.…”

Section: A Noise Versus Speedmentioning

confidence: 99%

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

Callens

Gielen

2021

IEEE Trans. Circuits Syst. I

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This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares the different ADC topologies for this 3D-stacked context in terms of noise, speed and power efficiency. The comparison shows that the ramp and incremental (I ) ADCs can achieve a better overall performance compared to the SAR and cyclic ADCs by a factor of ∼3 better for 3D-stacked CIS. In addition, ramp and I ADCs can both achieve (very) low fixed-pattern noise values.

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Section: A Noise Versus Speedmentioning

confidence: 99%

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

Callens

Gielen

2021

IEEE Trans. Circuits Syst. I

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Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Oliveira

Gomes

Fernández-Berni

et al. 2017

IEEE Trans. Circuits Syst. I

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Abstract-The paper addresses a comparison of architectures for hardware implementation of Gaussian image pyramids. Main differences between architectural choices are in the sensor frontend. One side is for architectures consisting of a conventional sensor that delivers digital images and which is followed by digital processors. The other side is for architectures employing a non-conventional sensor with per-pixel embedded pre-processing structures for Gaussian spatial filtering. This later choice belongs to the general category of "artificial retina" sensors which have been for long claimed as potentially advantageous for enhancing throughput and reducing energy consumption of vision systems. These advantages are very important in the internet of things context, where imaging systems are constantly exchanging information. The paper attempts to quantify these potential advantages within a design space in which the degrees of freedom are the number and type of ADCs (single-slope, SAR, cyclic, Σ∆ and pipeline), and the number of digital processors. Results show that speed and energy advantages of pre-processing sensors are not granted by default and are only realized through proper architectural design. The methodology presented for the comparison between focal-plane and digital approaches is a useful tool for imager design, allowing for the assessment of focal-plane processing advantages.

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A 2e_rms ⁻ Temporal Noise CMOS Image Sensor With In-Pixel 1/f Noise Reduction and Conversion Gain Modulation for Low Light Imaging

Priyadarshini

Sarkar

2021

IEEE Trans. Circuits Syst. I

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A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniques

Cited by 3 publications

References 8 publications

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

A 2e_rms ⁻ Temporal Noise CMOS Image Sensor With In-Pixel 1/f Noise Reduction and Conversion Gain Modulation for Low Light Imaging

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A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniques

Cited by 3 publications

References 8 publications

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

A 2erms − Temporal Noise CMOS Image Sensor With In-Pixel 1/f Noise Reduction and Conversion Gain Modulation for Low Light Imaging

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A 2e_rms ⁻ Temporal Noise CMOS Image Sensor With In-Pixel 1/f Noise Reduction and Conversion Gain Modulation for Low Light Imaging