A CMOS Subbandgap Reference Circuit With 1-V Power Supply Voltage

Sub 1 V CMOS bandgap reference design techniques: a survey

“…Some design techniques have consisted of implementing opamp with low input common mode voltage level by the use of BiCMOs technology [10]. In standard CMOS technology, the technique of partially forward biasing the source bulk junction of PMOS transistors while making sure that the opamp is maintained in the high gain region have been proposed [11,12]. Other design techniques of implementing sub 1 V BVR circuits are based on the usage of subthreshold transistors [12,13], in order to take advantage of their low threshold voltage capability, or by a combine usage of depletion mode and enhancement mode transistors [14], or by taking advantage of the difference in the gate work function material of transistors having different doping level and type [15].…”

“…Doyle et al [12] proposed a BVR circuit depicted in Fig. 13 that uses PMOS transistors with partially forward bias source bulk PN junction in combination with operation in the subthreshold region.…”

A Radiation Hard Bandgap Reference Circuit in a Standard 0.13 $\mu$m CMOS Technology

“…However, with steady progress in downscaling of CMOS technologies, the use of bandgap reference circuits with conventional diodes in radiation hard environments has two distinct disadvantages. Firstly, the low supply voltage in modern CMOS technologies significantly complicates the bandgap reference circuit design when conventional diodes are used [20]- [22]; a suitable approach using conventional diodes was introduced by Banba [23]. Secondly, it has been found that bandgap references featuring conventional diodes are rather vulnerable to TID effect [24].…”

Highly Reliable Non-volatile Logic Circuit Technology and Its Application

“…Since FE capacitors are isolated by disabled access driver except for turning on/off the power supply, performance of the NVFF is almost as same as that of the conventional FF during a logic operation. The access sequence for FE capacitors in all NVFFs is controlled by an NVFF controller jointly working with a reset IC or a power-on-reset (POR) circuit, which is used to detect turning on/off of the power supply [6], [7]. Since FE capacitors are accessed only when the NVFF controller detects a positive/negative edge of the reset signal, access times of FE capacitors are same to the cycles of power ON/OFF cycle.…”