A Clock and Data Recovery Circuit for the ALTAS/CMS HL-LHC Pixel Front End Chip in 65 nm CMOS Technology

Μουστάκας, Κωνσταντίνος; Rymaszewski, P.; Hemperek, T.; Krüger, H.; Vogt, M.; Wang, T.; Wermes, N.

doi:10.22323/1.370.0046

Cited by 4 publications

(4 citation statements)

References 4 publications

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“…The remaining SEE sensitivity of the proposed circuit has been clearly identified, and a mitigation strategy has been proposed, which will allow eliminating any circuit cross-section for phase errors exceeding 250 ps, below which the inductor radiation effect will remain as the dominant contributor. In terms of area, the proposed circuit approaches the area of ring oscillator PLLs manufactured in the same technology [33], mainly because of the large area occupied by the loop filter capacitor in analog PLLs, which is realized as a digital integrator in this design.…”

Section: Discussionmentioning

confidence: 99%

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

et al. 2021

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This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of −235 dB.

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Section: Discussionmentioning

confidence: 99%

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

et al. 2021

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“…This implies that the configuration memory, state machines, critical event data, look-up tables are all SEE robust. The on-chip CDR is SET hardened with triplicated clock divider, a bang-bang phase detector and an optimized voltage-controlled oscillator (VCO) [2]. As a means of having a small pixel size and staying within power dissipation constraints, the chip has different protection schemes for its pixel and global configuration memory which prevents soft errors at two different levels of efficiency [3].…”

Section: Rd53b Design For Soft Error Mitigationmentioning

confidence: 99%

Single event effects on the RD53B pixel chip digital logic and on-chip CDR

Lalic¹,

Fougeron²,

Madsen³

et al. 2022

J. Inst.

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The RD53B chip for HL-LHC upgrades of ATLAS and CMS pixel detectors needs to provide reliable operation in a radiation hostile environment with inevitable Single Event Effects (SEE). To answer the challenge, substantial efforts are made to protect and evaluate the critical parts of the digital logic and to characterize the on-chip Clock and Data Recovery (CDR) circuit. The SEE sensitivity of the digital logic is evaluated by testing with both heavy-ions and protons. The on-chip CDR is characterized by measuring the SEE-induced phase shifts of its output clocks and their implication on the high-speed link stability.

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“…It is a mixed signal chip, having both analogue and digital circuits. It features custom-designed intellectual property blocks, such as clock data recovery and phase locked loop blocks [15] for the clock recovery from the command stream running at 160 Mb/s; a high speed output transmitter with a current mode logic cable driver [16] sending data at 1.28 Gb/s on up to four output lanes; and a shunt low-dropout regulator [17] for serial powering of the pixel modules. The chip size is 20.0 × 11.8 mm 2 , which is about half the size of the final chip, as it shares the chip reticle with CMS Outer Tracker chips.…”

Section: Rd53a Analogue Front-endsmentioning

confidence: 99%

Comparative evaluation of analogue front-end designs for the CMS Inner Tracker at the High Luminosity LHC

et al. 2021

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The CMS Inner Tracker, made of silicon pixel modules, will be entirely replaced prior to the start of the High Luminosity LHC period. One of the crucial components of the new Inner Tracker system is the readout chip, being developed by the RD53 Collaboration, and in particular its analogue front-end, which receives the signal from the sensor and digitizes it. Three different analogue front-ends (Synchronous, Linear, and Differential) were designed and implemented in the RD53A demonstrator chip. A dedicated evaluation program was carried out to select the most suitable design to build a radiation tolerant pixel detector able to sustain high particle rates with high efficiency and a small fraction of spurious pixel hits. The test results showed that all three analogue front-ends presented strong points, but also limitations. The Differential front-end demonstrated very low noise, but the threshold tuning became problematic after irradiation. Moreover, a saturation in the preamplifier feedback loop affected the return of the signal to baseline and thus increased the dead time. The Synchronous front-end showed very good timing performance, but also higher noise. For the Linear front-end all of the parameters were within specification, although this design had the largest time walk. This limitation was addressed and mitigated in an improved design. The analysis of the advantages and disadvantages of the three front-ends in the context of the CMS Inner Tracker operation requirements led to the selection of the improved design Linear front-end for integration in the final CMS readout chip.

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A Clock and Data Recovery Circuit for the ALTAS/CMS HL-LHC Pixel Front End Chip in 65 nm CMOS Technology

Cited by 4 publications

References 4 publications

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

Single event effects on the RD53B pixel chip digital logic and on-chip CDR

Comparative evaluation of analogue front-end designs for the CMS Inner Tracker at the High Luminosity LHC

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