Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

Biereigel, Stefan; Kulis, Szymon; Moreira, P.; Koelpin, Alexander; Leroux, Paul; Prinzie, Jeffrey

doi:10.3390/electronics10222741

Cited by 7 publications

(6 citation statements)

References 31 publications

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“…Subsequently, only the tracking bank is used during closed-loop operation. Further design details can be found in [6].…”

Section: Digitally Controlled Lc Oscillatormentioning

confidence: 99%

“…Only at the highest LET Si could transients exceeding the random jitter of the PLL be detected [8]. The cross section of the LC ADPLL is much larger in comparison, and the root causes for this sensitivity in the LC DCO have been identified in the used inductor geometry and the switched-capacitor cells used in the PVT and acquisition banks, as discussed in [6,13].…”

Section: Single-event Effects Testingmentioning

confidence: 99%

“…The LC DCO in comparison showed a radiation-induced frequency shift of less than 1%. The LC ADPLL failed to operate reliably at a dose of 1.4 Grad due to a failure of its divide-by-two prescaler circuit [6].…”

Section: Jinst 18 C01060mentioning

confidence: 99%

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Radiation-tolerant all-digital clock generators for HEP applications

Biereigel¹,

Kulis²,

Mendes³

et al. 2023

J. Inst.

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The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening considerations, as well as the performance obtained with these circuits are presented in this article.

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“…Subsequently, only the tracking bank is used during closed-loop operation. Further design details can be found in [6].…”

Section: Digitally Controlled Lc Oscillatormentioning

confidence: 99%

Section: Single-event Effects Testingmentioning

confidence: 99%

See 1 more Smart Citation

Radiation-tolerant all-digital clock generators for HEP applications

Biereigel¹,

Kulis²,

Mendes³

et al. 2023

J. Inst.

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“…Therefore, CMOS devices are susceptible to Single Event Effect (SEE) [3][4][5][6]. In particular, Single Event Latch-up (SEL), a special SEE, can alter devices' currents and even cause devices to burn up in severe cases [7][8][9][10]. From a circuit-level hardness perspective, SEL is generated by the conduction of parasitic PNP and NPN transistors inside the devices, creating low resistance paths between the devices' power supplies and grounds with resulting devices' current rise when the devices are exposed to the space radiation [11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Xin

Zhu

et al. 2023

Electronics

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Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

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“…The circuits are implemented in 65 nm CMOS technology and feature different radiation-hardening techniques. Paper [5] presents the first fully integrated radiation-tolerant all-digital phase-locked loop (ADPLL) and clock and data recovery (CDR) circuit for wireline communication applications. Several radiationhardening techniques are proposed to achieve state-of-the-art immunity to SEEs up to 62.5 MeV cm 2 mg −1 as well as a 1.5 Grad TID tolerance.…”

mentioning

confidence: 99%