The realisation of the Timepix3 chip opened the way for new opportunities in research areas such as particle tracking with both semiconductor sensors and gas filled time projection chambers, electron microscopy and imaging mass spectrometry.To exploit the full capability of the Timepix3 chip, Nikhef developed a compact read-out system, called SPIDR that can deal with the high data output of 80 Mhits per chip per second. The main read-out board connects to both 10 Gb Ethernet and 1 Gb Ethernet devices. The latter obviously at a reduced rate. The main board connects to individual chip-carrier boards via a standard FMC connector. The system is designed such that support for other readout chips is foreseen via reprogramming of the FPGA. Besides the Timepix3 chip also the Medipix3 chip is currently supported.Both the main board and the chip carrier boards are cooled, via the housing and a fan to obtain a stable temperature of around 40 ± 0.2 ˚C for the Timepix3 chips. We will present the system and the results obtained with the LHCb beam telescope at CERN and proton radiography data obtained with a time projection chamber based on GEM technology. K: Electronic detector readout concepts (gas, liquid); Modular electronics; Electronic detector readout concepts (solid-state); Front-end electronics for detector readout 1Corresponding author.
The LHCb VELO Timepix3 telescope is a silicon pixel tracking system constructed initially to evaluate the performance of LHCb VELO Upgrade prototypes. The telesope consists of eight hybrid pixel silicon sensor planes equipped with the Timepix3 ASIC. The planes provide excellent charge measurement, timestamping and spatial resolution and the system can function at high track rates. This paper describes the construction of the telescope and its data acquisition system and offline reconstruction software. A timing resolution of 350 ps was obtained for reconstructed tracks. A pointing resolution of better than 2 µm was determined for the 180 GeV/c mixed hadron beam at the CERN SPS. The telescope has been shown to operate at a rate of 5 million particles s −1 · cm −2 without a loss in efficiency.
Timepix3 is a hybrid pixel detector readout chip. It features a data driven readout mode where the chip sends out a data packet containing pixel coordinate, time over threshold and time of arrival immediately after the hit is processed by the pixel. The maximum hit rate is 40 Mhits/cm 2 /s with a minimum time step in the arrival time measurement of 1.56 ns. The pixel matrix consist of 256 × 256 square pixels at a 55 µm pitch and the pixel front end noise is 61 e − RMS. In this paper we present the first radiation measurements with Timepix3 bump bonded to a 300 µm thick silicon sensor. The chip is calibrated per pixel, using internal test pulses and the calibration is verified using X-ray fluorescence. The energy resolution, threshold dispersion and gain dispersion is measured. The energy resolution in time over threshold mode under normal operation conditions is 4.07 keV FWHM at 59.5 keV. At 10.5 keV an energy resolution of 0.72 keV FWHM was achieved in photon counting mode and in time over threshold mode, by optimizing the energy response, we achieved a 1.38 keV FWHM. We also investigate the time walk and present first results on using the time information for track reconstruction.
This paper describes a front-end for hybrid pixel readout chips, which was developed for the Timepix3 and Smallpix ASICs. The front-end contains a single-ended preamplifier with a structure for leakage current compensation which can handle both signal polarities, and a single-threshold discriminator with compensation for pixel-to-pixel mismatch. Preamplifier and discriminator are required to be fast, to allow a Time-Of-Arrival (TOA) measurement with a resolution of 1.56 ns. Time-Over-Threshold (TOT) is also measured; the monotonicity of TOT with respect to the input charge is greatly improved as compared to the previous Timepix chip. The analog area is only 55 μm × 13.5 μm. Timepix3 has already been fabricated and the first test results are also presented in this paper.
A prototype hybrid pixel detector ASIC specifically designed to the requirements of the vertex detector for CLIC is described and first electrical measurements are presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64 × 64 square pixels with 25 µm pitch. The main features include simultaneous 4-bit measurement of Time-over-Threshold (ToT) and Time-of-Arrival (ToA) with 10 ns accuracy, on-chip data compression and power pulsing capability.
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