A Carry-Free Multiplication Implementation Method

Abstract

Delay caused by carry propagation is an unfavourable issue that much affects the efficiency of numerical computing in computer system. And the more data bits of the operands, the worse the delay. As data bits of the operands in optical computer can be huge because of the high information capability of light, this makes carry delay be very serious. As multiplication is one of the most important and popular calculations and many multiplications can be carried out in parallel by utilizing huge number of data bits of optical computer, study on how to reduce or even mitigate carry delay in multiplication is very important. To improve the multiplication efficiency, a new carry free method to design and implement multiplication based on Ternary Optical Computer (TOC) is put forward. Fully considering the relations between the operands based on modified signed-digit (MSD) number system, a parallel mulitplication implemeation strategy together with its resource allocation method is presented. The experimental results show that the proposed strategy is correct. It exerts the advantages of optical computing and ensures that no carry delay is introduced in the process of multiplication which much improves the efficiency of optical multiplication applications. INDEX TERMS Carry-free, MSD number system, multiplication application, optical computing.

Algorithm on Higher-Order Derivative Based on Ternary Optical Computer

“…If m is an even number, the first layer needs to construct (m + 1)/2 multipliers, and the second layer needs to construct (m + 1)/2 2 multipliers; the i-th layer needs to construct (m + 1)/2 i multipliers, and a total of log 2 (m + 1) columns need to be constructed, so for a single coefficient, the multiplier that needs to be constructed is [41]…”

“…The data bit analysis is performed with the higher-order derivative function f m (a). The maximum exponent is b i , when b i is even, the number of multipliers that need to be constructed in the first layer is (b i + 1)/2 ; the second layer needs to construct (b i + 1)/2 2 multipliers [7], and the j-th layer needs to construct (b i + 1)/2 j multipliers [41]. A total of log 2 (b i + 1) columns need to be constructed, and the number of multipliers corresponding to a single coefficient is…”

Hardware‐efficient approximate logarithmic division with improved accuracy

“…In modern era, the processor deals with complex arithmetic operations which need advanced addition, multiplication, and division units 1‐6. Many algorithms are proposed for advanced adders and multipliers, while division is getting less dealt.…”