A Capped Trimming Hard-Mask Patterning Technique for Integration of Nano-Devices and Conventional Integrated Circuits

Wu, Xusheng; Chan, Peggy; Zhang, Shengdong; Chan, Mansun

doi:10.1109/edssc.2005.1635393

Cited by 2 publications

(1 citation statement)

References 11 publications

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“…The SCEs can be reduced using an inversion layer as an ultra shallow source/drain (S/D) in the sub-50 nm regime. [10][11][12][13][14][15][16] Furthermore, in ref. 17, an analytical model of the surface potential and threshold voltage of a SOI MOSFET with electrically induced shallow S/D junctions has been presented to investigate the SCEs.…”

Section: Introductionmentioning

confidence: 99%

Two-Dimensional Analytical Modeling of Fully Depleted Short-Channel Dual-Gate Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

Anvarifard¹,

Hosseini²,

Armaki³

2009

Jpn. J. Appl. Phys.

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In this paper, a two-dimensional (2D) analytical model of the surface potential variation along the channel in a fully depleted dual-gate (DG) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed to investigate short-channel effects (SCEs). Our model includes the length of the two gates and the voltage difference between them. We demonstrate that the surface potential in the channel region exhibits a step function, which causes the screening of the drain potential. This results in suppressed SCEs such as the hot-carrier effect and drain-induced barrier lowering (DIBL). The obtained results of our model are compared with those of the single-gate (SG) SOI MOSFET, and the DG SOI MOSFET performance is found to be superior.

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