Two-Dimensional Analytical Modeling of Fully Depleted Short-Channel Dual-Gate Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

Abstract

In this paper, a two-dimensional (2D) analytical model of the surface potential variation along the channel in a fully depleted dual-gate (DG) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed to investigate short-channel effects (SCEs). Our model includes the length of the two gates and the voltage difference between them. We demonstrate that the surface potential in the channel region exhibits a step function, which causes the screening of the drain potential. This results in suppressed SCEs such as the hot-carrier effect and drain-induced barrier lowering (DIBL). The obtained results of our model are compared with those of the single-gate (SG) SOI MOSFET, and the DG SOI MOSFET performance is found to be superior.

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

“…As the length of the channel decreases, the gate control over the channel region reduces which leads to various short channel effects (SCEs). 4,5 To eliminate these effects, several new device topologies were proposed including fully depleted SOI-MOSFETs, dual-gate (DG) MOSFETs, and multigate (MG) MOSFETs.…”