Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

Abstract

This paper presents a performance analysis of 3-stack JL-NWFETs with different spacer materials and spacer lengths. The DC and analog/RF performance is analysed at the device level, and circuit level. In single-k spacer analysis, TiO2 exhibits lowest IOFF of ~89.28%, and largest ION/IOFF ratio with better subthreshold performance of ~42.51% as compared to Air spacer at Lext= 7nm. In addition, TiO2 spacer is suitable for analog applications while Air spacer for RF applications. The dual-k spacer analysis is also performed and the TiO2+Air spacer showed prodigious DC/Analog/RF performances dominating all other combinations. Further investigations into inner high-k spacer analysis (Lsp,hk) revealed that higher Lsp,hk is suitable for DC and Analog applications whereas lower Lsp,hk for RF applications. The CS amplifier designed for configurations of Lsp,hk showed better gain for higher Lsp,hk with the amplification gain of ~4.8V/V. Overall, this analysis serves as a beacon, guiding the future of JL-NWFET design for spellbinding nano-electronic devices at sub-5nm technology node.