A new transistor of dual-gate SOI and evidence for diminished short channel effects

Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL

“…Moreover, in the case of different V DS , the linear slope can be considered approximately equal. Other than a step function of front-surface potential proposed by (Anvarifard et al 2009), we observed from Fig. 6 that the front-surface potential is a continuous function.…”

“…Therefore, the DIBL is suppressed to a extent. Moreover, a conclusion is drawn from the numerical simulation that despite being controlled by the different gate voltages, the front-surface potential of this UTBB SOI device is a continuous function, rather than a step function proposed by (Anvarifard et al 2009). This device structure is valid not only for UTBB SOI transistors, but also generally useful for the vertical independent double-gate and gate-all-around devices featuring a lightly-doped channel.…”

“…The SCEs, which mainly includes the threshold voltage roll-off, the drain induced barrier lowering (DIBL), and the subthreshold swing degradation, is the major barrier for MOSFET downscaling. Therefore, based on the UTBB SOI technology, a number of methods have been proposed to further reduce the SCEs, by employing the channel engineering, the source/drain engineering (Yamada et al 2013b, c;Srivastava et al 2016), the back-biasing technique (Burignat et al 2010;Karatsori et al 2015), the thickness modulation of the buried oxide layer (Yamada et al 2013a), and the gate voltage difference engineering (Anvarifard et al 2009;Anvarifard and Orouji 2013;Lahgere et al 2015).…”