2020 IEEE International Electron Devices Meeting (IEDM) 2020
DOI: 10.1109/iedm13553.2020.9371944
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A Back Illuminated 10μm SPAD Pixel Array Comprising Full Trench Isolation and Cu-Cu Bonding with Over 14% PDE at 940nm

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Cited by 22 publications
(36 citation statements)
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“…Despite the degradation of the PDE by metal reflections, the presented FSI device achieves a competitive NIR PDE. Additionally, P ap exceeds the state-of-the-art [8] due to the small active region. Unlike typical SPADs with thick depleted absorption volumes [19], the device is compatible with a standard CMOS readout (enabled by V e = 3.5 V), and the pitch is not limited by a guard ring.…”
Section: Discussionmentioning
confidence: 94%
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“…Despite the degradation of the PDE by metal reflections, the presented FSI device achieves a competitive NIR PDE. Additionally, P ap exceeds the state-of-the-art [8] due to the small active region. Unlike typical SPADs with thick depleted absorption volumes [19], the device is compatible with a standard CMOS readout (enabled by V e = 3.5 V), and the pitch is not limited by a guard ring.…”
Section: Discussionmentioning
confidence: 94%
“…The lack of isolation negatively affects the NIR timing resolution and crosstalk of the FSI SPAD, as is the case for other nonisolated SPADs [14,18]. However, since the absorption volume is depleted, back-side illumination (BSI) and deep-trench isolation (as in [8]) can greatly improve isolation while enhancing the PDE and timing resolution. Additionally, V bd < 40 V and a lower R r can be obtained when reducing the epi thickness and optimizing the doping.…”
Section: Discussionmentioning
confidence: 99%
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“…Yet, the most recent advance in CMOS technology for dToF is 3D-stacking with face to face bonding of top-tier BSI SPAD wafer with an advanced digital CMOS wafer bottom-tier (3D-BSI) [39]. The BSI SPAD is placed directly above the pixel circuit, a recent example showing a 90nm 1ML / 45nm 11ML stack is given in [40]. There are further benefits to stacked technology for dToF: cost reduction or performance increase and independent technology development and optimization of digital CMOS and SPAD diode processes.…”
Section: A Technology Trendsmentioning
confidence: 99%