A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS

Cao, Yuefeng; Zhang, Shumin; Zhang, Tianli; Chen, Yongzhen; Zhao, Yutong; Chen, Chixiao; Ye, Fan; Ren, Junyan

doi:10.1109/tcsi.2020.3037295

Cited by 16 publications

(9 citation statements)

References 38 publications

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“…As shown in Table 2 , state-of-the-art background calibrations are listed. Compared to [ 11 , 12 ], this work and [ 13 ] are signal-independent. To achieve signal independence, ref.…”

Section: Simulation Results and Comparisonmentioning

confidence: 99%

“…[ 13 ] requires complex shuffling and two-bit inter-stage redundancy, while, in this work, an auxiliary capacitor array with PN pre-injection technique realizes simple shuffling and occupies little residue headroom. The convergence cycles are less than [ 11 ], but more than [ 12 , 13 ]. Although the signal elimination in the proposed calibration can speed up convergence, there is mismatch between sub-ADC and main ADC, and this means that the signal cannot be estimated as accurately as in [ 12 , 13 ].…”

Section: Simulation Results and Comparisonmentioning

confidence: 99%

“…Moreover, the signal independence increases the signal interference and, thus, decreases the algorithm’s convergence speed. The split-ADC calibration [ 12 ], where the ADC is divided into two identical half-ADCs to convert the input signal into different paths, exploits the outputs’ difference to eliminate the signal interference, and, therefore, increases the convergence speed, although it incurs more area and power consumption since the parasitic effect and logic circuit almost double. Sharing the first stage with two second stages in [ 13 ] achieves the same acceleration effect as split-ADC, but the residue requires two amplifications, which reduces the ADC speed.…”

Section: Introductionmentioning

confidence: 99%

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Signal-Independent Background Calibration with Fast Convergence Speed in Pipeline-SAR ADC

Wang

Wan

et al. 2023

Micromachines

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This brief proposes a signal-independent background calibration in pipeline-SAR analog-to-digital converters (ADCs) with a convergence-accelerated technique. To achieve signal independence, an auxiliary capacitor array CA is introduced to pre-inject a pseudo-random noise (PN) in the sampling phase to cancel out the opposite PN injection of the calibrated capacitor in the conversion phase, and CA is also used to realize the D/A function of the calibrated capacitor in the conversion phase. In this way, no matter what the signal is, the residue headroom remains unchanged even with PN injection. Moreover, the first sub-ADC is designed with extended conversion bits to quantize its own residue after delivering the conversion bits required by the first stage. Afterwards, this result is provided to the calibration algorithm to reduce the signal component and accelerate the convergence. Based on the simulation, the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) improve from 45.3 dB and 56.4 dB to 68.2 dB and 88.4 dB, respectively, after calibration. In addition, with the acceleration technique, convergence cycles decrease from 1.7 × 108 to 5.8 × 106. Moreover, no matter whether the input signal is DC, sine wave or band-limited white noise, the calibration all works normally.

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“…As shown in Table 2 , state-of-the-art background calibrations are listed. Compared to [ 11 , 12 ], this work and [ 13 ] are signal-independent. To achieve signal independence, ref.…”

Section: Simulation Results and Comparisonmentioning

confidence: 99%

Section: Simulation Results and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Signal-Independent Background Calibration with Fast Convergence Speed in Pipeline-SAR ADC

Wang

Wan

et al. 2023

Micromachines

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“…The prototype ADC, fabricated in a 130 nm CMOS process, can achieve a SNR of 69.1 dB and a SNDR 80.7 dB. In order to increase the conversion rate and also reduce power consumption, Cao et al [69] proposed a singlecoarse dual-fine pipelined-SAR ADC with split-based background calibration, as shown in Figure 18c. The shuffle mechanism, which can effectively avoid the divergence of the traditional algorithms in digital background correction based on split ADC, is employed in the architecture.…”

Section: Hybrid Adcmentioning

confidence: 99%

A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System

et al. 2022

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As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.

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“…In addition, many of the optimization techniques applied to SAR ADCs can also be applied to multi-stage pipeline-SAR ADCs, such as efficient switching schemes [18][19][20], redundant trails in SAR conversion, which alleviate the requirements for comparator offset and MSB settlement [21]. Finally, as digital circuits benefit more from process development, more designs tend to use digital calibration methods to compensate for analog circuits, such as split-channel-based architectures that can calibrate both capacitor arrays and amplifiers [22].…”

Section: Pipelined-sar Adcmentioning

confidence: 99%

A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution

Ren

2022

Electronics

Self Cite

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This paper presents a calibration-free, 16-channel, 14-bit, 50-MS/s, pipelined successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) for ultrasound imaging systems. A reference sharing scheme with reduced buffers is proposed to improve area-and-power efficiency, which is essential for multi-channel systems. Based on this, a three-stage, pipelined-SAR ADC architecture with reference/op-amp sharing and optimized stage resolution distribution is proposed. The prototype ADC is designed in a 0.18-μm process with peripheral circuits integrated, including low-voltage differential signaling (LVDS), bandgap, etc. It achieves a robust and calibration-free performance with 68.25-dB signal to noise and distortion ratio (SNDR) and 82.19-dB spurious-free dynamic range (SFDR), translating into a competitive figure of merit (FoM) of 0.47 pJ/conversion-step among other high-resolution ADCs used in ultrasound applications.

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A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS

Cited by 16 publications

References 38 publications

Signal-Independent Background Calibration with Fast Convergence Speed in Pipeline-SAR ADC

Signal-Independent Background Calibration with Fast Convergence Speed in Pipeline-SAR ADC

A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System

A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution

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