A 75 pJ/bit all-digital quadrature coherent IR-UWB transceiver in 0.18 µm CMOS

Barajas, E.; Gomez, Didac; Mateo, D.; González, José

doi:10.1109/rfic.2010.5477250

Cited by 4 publications

(3 citation statements)

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“…The first step is to choose the delay cell architecture and the ratio of the transistors involved. The delay cell examined in this paper is a scaled version of the one presented in [14]. It's a fully differential (complementary) structure whose delay can be controlled by means of the supply voltage of an inverter.…”

Section: B Vcdl Block Modelmentioning

confidence: 99%

Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption

Barajas

Mateo

González

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Abstract-This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation.Index Terms-DLL, CMOS, behavioural, modelling, Verilog-A, optimisation I. INTRODUCTION During the last years the scaling of the CMOS technology has allowed the integration of full systems on a chip (SoC), including both the digital and analog blocks, as well as the RF front-end [1], [2]. However new design difficulties have arose due to this decreasing transistor dimensions [3]- [5]. As it will be demonstrated, once the delay-locked loop (DLL) architecture and size (number of cells) has been fixed, the actual dimensions of the DLL blocks have a great impact on the performance of the system.The theoretical jitter analysis of all the main contributors to the output jitter has been done for PLL/DLL systems [6], [7]. Also, the transistor level jitter analysis has been carried out for the charge pump [8] and the voltage controlled delay line [9], [10]. This theoretical models have allowed to predict the jitter performance of the DLL blocks and their contribution to the total output jitter. However, their limited accuracy has led to the use of behavioural models based on transistor level simulations, for both PLLs [11] and DLLs [12]. But, even with these latter models, the task to methodically analyse the system for a wide range of dimensions is a very time consuming procedure. This prevents to obtain an accurate model for the DLL jitter performance and the power consumption.In this paper a new fast behavioural model to analyse the impact of the physical transistor dimensions on the overall performance of a DLL is developed. In section II an introduction to the main sources of jitter in a DLL is carried out, while in section III a behavioural model for the DLL blocks is developed. The basis for fast model DLL simulation are explained in section IV. Finally, the results obtained with the introduced model are analysed and discussed in section V.

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Section: B Vcdl Block Modelmentioning

confidence: 99%

Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption

Barajas

Mateo

González

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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“…Barajas et al. presented a high‐speed IR‐transmitter in a 180‐nm CMOS process; however, it had high power consumption and area. Casu et al.…”

Section: Introductionmentioning

confidence: 99%

A very low complexity IR‐UWB transmitter with BPSK modulation for balanced antenna

Khalesi

Nabavi

Mirzakouchaki

2014

IEEJ Transactions Elec Engng

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A very low complexity impulse radio‐ultrawideband (IR‐UWB) transmitter suitable for balanced antenna is presented. This all‐digital transmitter employs the binary phase‐shift keying (BPSK) modulation scheme and eliminates the need for a balun. Also, a new Gaussian monocycle pulse generator is proposed which is used as impulse transmitted signal. The transmitter circuit was designed in 0.18‐μm complementary metal–oxide–semiconductor technology. The post‐simulation results show that the core chip size was only 0.02 mm2. The output amplitude pulse yielded 150 mV peak‐to‐peak under a supply voltage of 1.8 V. Simulation results show that the transmitter consumes 8.5 pJ/pulse for 200‐MHz pulse repeating frequency. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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“…Οι υλοποιιςεισ [94], [95], [96] υποςτθρίηουν BPSK διαμόρφωςθ και ο λεπτόσ τετραγωνικόσ παλμόσ παράγεται με χριςθ απαρικμθτϊν, γεγονόσ που κζτει περιοριςμοφσ ςτθν ανεξάρτθτθ επιλογι τθσ διάρκειασ του παλμοφ ςε ςχζςθ με τθν PRF. Στο [97] ζχουν χρθςιμοποιθκεί IQ μονοπάτια και ο τετραγωνικόσ παλμόσ είναι θ ίδια θ παλμοςειρά των δεδομζνων. Θ ενεργειακι αποδοτικότθτα είναι ςτα και ο μζγιςτοσ ρυκμόσ .…”

Section: Reconstructionunclassified

Σχεδιάση Και Ανάπτυξη Ολοκληρωμένων Κυκλωμάτων Για Συστήματα Υπερευρείας Ζώνης Με Έμφαση Στα Κυκλώματα Του Πομπού

Παπαμιχαήλ¹

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The multitude of applications that Ultra-Wideband (UWB) technology can serve, from highspeed Wireless Personal Area Networks to Wireless Sensor Networks with precision Geolocation abilities, has attracted intense research interest in the implementation of UWB systems. The unusually wide range of frequencies assigned to UWB, from , allows UWB systems employing low order modulation schemes to enjoy high throughput at low power consumption. According to the foregoing assignment, however, UWB shares the spectrum with existing wireless networking technologies, and, thus, UWB emissions must be limited to a power spectral density below the threshold of , satisfying very stringent emission masks and introducing great challenges in the design of low power and small area transmitters.The subject of this thesis is the design of low power, fully integrated, CMOS UWB transmitters (TXs), with high spectral flexibility, high speed and high modulation quality. Due to the low power requirements, this work focused on the Impulse Radio technology, while the high spectral flexibility was partially addressed by a Multi-Band architecture, based on Up-Conversion. The resulting Multi-Band Impulse-Radio (MB-IR) TX architecture employs Gaussian baseband pulse shaping and Direct Sequence BPSK modulation.The key contributions of this thesis are a CMOS Gaussian Pulse Generator and a BSPK modulation topology, which jointly constitute a high performance analog baseband unit, and lead to a reconfigurable, low power, low EVM, Gigabit MB-IR UWB transmitter RFIC, which is FCC/ECC mask compliant without the need for any off-chip components.The novel Pulse Generator (PG) is based on non-linear shaping, so as to facilitate the configurability of the output pulse duration, and exploits the voltage transfer characteristic of a Resistive Loaded Asymmetrical CMOS Inverter (RLACI), which results in spectral sidelobes typically better than . The PG incorporates low voltage circuits of digital nature, while the MOSFET devices that undertake the pulse shaping avoid exclusive operation in weak inversion, in contrast to previous implementations. Consequently, the proposed CMOS PG is able to support higher throughput, as well as higher output amplitude, which relaxes considerably the design of the RF front end.

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A 75 pJ/bit all-digital quadrature coherent IR-UWB transceiver in 0.18 µm CMOS

Cited by 4 publications

References 8 publications

Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption

Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption

A very low complexity IR‐UWB transmitter with BPSK modulation for balanced antenna

Σχεδιάση Και Ανάπτυξη Ολοκληρωμένων Κυκλωμάτων Για Συστήματα Υπερευρείας Ζώνης Με Έμφαση Στα Κυκλώματα Του Πομπού

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