A 700-MHz switched capacitor analog waveform sampling circuit

Abstract

IntroductionAnalog switched capacitor memory devices are suitable for use in a wide range of applications where analog waveforms and signals must be captured or delayed, such as the recording of pulse echo events (RADAR, Ultrasonics) and pulse shape recording (high energy physics experiments). A switched-capacitor analog memory circuit intended for use in high-speed, low-power data acquisition systems operating at frequencies up to 700 MHz is described. The circuit can be used to measure the positions of a high energy electron beam along an accelerator, where waveforms from hundreds of beam position seflsors must be sampled at rates in excess of 500 MHz. A two-channel version of the circuit with 32 memory cells for each channel has been integrated in a 2-pm CMOS technology with poly-poly capacitors. One memory channel dissipates 0.9 mW while operating from a single +J V supply. Circuit DescriptionA simplified schematic of one memory channel is shown in Figure. 1. Each memory cell consists of a sampling (write) transistor (Mwi), a minimum-size read transistor (M .), and a storage capacitor. The area of a memory cell is 40 x 40 pm and is dominated by the 0.5 pF capacitor and the sampling switch (W/L.=50 pm/2 pm). Analog signals are sampled in the circuit at a high rate and the stored information is subsequently read out at a lower speed. During data acquisition, transistor MJ~J is turned on, connecting the signal to the input bus, while transistor MOrrr and the read switches M R~ through MR32 are all off, isolating the input bus. An analog signal applied at the circuit's input is sampled onto the cell capacitors Ci by sequentially turning transistors Mwl through Mw32 on and off. Samples of the input waveform at 32 discrete times are thereby stored in the memory channel. During read-out, transfer gate Mm is turned off while hW and M R~T are turned on, forcing the input bus to Vsms. M~T is then tumed off and the voltage stored in the first cell is read out by turning transistor MRI on. After the output has settled, the signal may be digitized with an external low-speed, low-power converter. After digitization MRI is tumed off and MRST is again tumed on, which forces the input bus back t o V, , , .The cycle is repeated for all cells. The principal performance issues for the intended application are low cell-to-cell offset, gain, and sample time variations across a channel, all of which are governed by the circuit architecture and its sensitivity to the matching properties of its constituent transistors and capacitors. In the architecture presented here, the cell-tocell response variations are dominated by charge injection during turn-off of the write transistors. The resulting cell pedestals do not depend on the input signal level (as in [1]-[3]) and can be accurately determined and then cancelled by means of either analog or digital subtraction. Furthermore, the turn-off time of the sampling switches is independent of the input signal level, eliminating the timing errors that would require extensive data correction a...

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