Initial characterization and partial purification of thymic dendritic cells (DC) from miniature swine were carried out with the ultimate goal of using these cells to induce transplantation tolerance in this preclinical animal model. Immunohistochemical analysis of swine thymic tissue sections has shown DC to be large cells located in the medullary and the cortico-medullary regions as evidenced by the presence of surrounding Hassal bodies. These cells exhibit membrane processes and express the CD1, granulocyte/macrophage (G/M), and major histocompatibility complex (MHC) class II surface antigens, as well as the S100 cytosolic and nuclear markers found in humans to be specific for DC. Dendritic cells were purified from thymi following collagenase treatment, Percoll gradient centrifugation, and adhesion steps to plastic. Cells similar in morphology and phenotype to those described in tissue sections were detected in the lighter density layers of the gradient and represented 0.02% of the starting cell number. Removal of plastic nonadherent cells showed enrichment levels similar to those reported for murine and human DC. Two-colour flow cytometric analysis of purified pig DC identified these cells as MHC class IIhi, CD1+, CD2+, and G/M+. The dendritic nature of these cells was confirmed by their potent ability to stimulate alloreactive T lymphocytes. Modification of porcine thymic DC by transfer of allogeneic MHC genes and reinjection into the DC donor should permit testing of the role of this DC subset in the induction of transplantation tolerance.
IntroductionAnalog switched capacitor memory devices are suitable for use in a wide range of applications where analog waveforms and signals must be captured or delayed, such as the recording of pulse echo events (RADAR, Ultrasonics) and pulse shape recording (high energy physics experiments). A switched-capacitor analog memory circuit intended for use in high-speed, low-power data acquisition systems operating at frequencies up to 700 MHz is described. The circuit can be used to measure the positions of a high energy electron beam along an accelerator, where waveforms from hundreds of beam position seflsors must be sampled at rates in excess of 500 MHz. A two-channel version of the circuit with 32 memory cells for each channel has been integrated in a 2-pm CMOS technology with poly-poly capacitors. One memory channel dissipates 0.9 mW while operating from a single +J V supply. Circuit DescriptionA simplified schematic of one memory channel is shown in Figure. 1. Each memory cell consists of a sampling (write) transistor (Mwi), a minimum-size read transistor (M .), and a storage capacitor. The area of a memory cell is 40 x 40 pm and is dominated by the 0.5 pF capacitor and the sampling switch (W/L.=50 pm/2 pm). Analog signals are sampled in the circuit at a high rate and the stored information is subsequently read out at a lower speed. During data acquisition, transistor MJ~J is turned on, connecting the signal to the input bus, while transistor MOrrr and the read switches M R~ through MR32 are all off, isolating the input bus. An analog signal applied at the circuit's input is sampled onto the cell capacitors Ci by sequentially turning transistors Mwl through Mw32 on and off. Samples of the input waveform at 32 discrete times are thereby stored in the memory channel. During read-out, transfer gate Mm is turned off while hW and M R~T are turned on, forcing the input bus to Vsms. M~T is then tumed off and the voltage stored in the first cell is read out by turning transistor MRI on. After the output has settled, the signal may be digitized with an external low-speed, low-power converter. After digitization MRI is tumed off and MRST is again tumed on, which forces the input bus back t o V, , , .The cycle is repeated for all cells. The principal performance issues for the intended application are low cell-to-cell offset, gain, and sample time variations across a channel, all of which are governed by the circuit architecture and its sensitivity to the matching properties of its constituent transistors and capacitors. In the architecture presented here, the cell-tocell response variations are dominated by charge injection during turn-off of the write transistors. The resulting cell pedestals do not depend on the input signal level (as in [1]-[3]) and can be accurately determined and then cancelled by means of either analog or digital subtraction. Furthermore, the turn-off time of the sampling switches is independent of the input signal level, eliminating the timing errors that would require extensive data correction a...
Hemangiopericytomas are rare tumors of the head and neck. The benign presentation of this tumor belies its high local recurrence rate, local aggressiveness, and malignant potential. In view of these characteristics, workup to provide a diagnosis preoperatively is of significant importance. Diagnostic imaging is helpful in planning operative management, detecting metastases, and narrowing the list of differential diagnoses. However, because of the variety and lack of specificity of radiologic findings, it is generally difficult to provide a diagnosis. A history of a painless, slowly growing, otherwise asymptomatic mass, together with the radiologic findings of a vascular neoplasm, should enhance the suspicion of an HPC as a diagnosis. Hemangiopericytoma should be included in the differential diagnosis of any vascular soft tissue lesion presenting in the head and neck, and plans for surgical intervention should include the possibility of aggressive, wide local resection in order to adequately treat such a lesion should it be encountered.
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