A Low-Power Receiver with Switched-Capacitor Summation DFE

Emami, Azita; Varzaghani, A.; Bulzacchelli, John F.; Rylyakov, Alexander V.; Yang, Chih-Kong Ken; Friedman, Daniel

doi:10.1109/vlsic.2006.1705375

Cited by 6 publications

(3 citation statements)

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“…In a DFE, the results of the decision of previously received symbols have to be fed back to the current symbol before it is decided whether the current symbol is "1" or "0" [4]. Therefore the delay of the feedback loop has to be smaller than 1-UI to compensate the ISI at the center of the data eye, that is, the data sample [5]. The amount of the ISI at the edge of the data eye may be different from that of the ISI at the center of the data eye.…”

Section: Introductionmentioning

confidence: 99%

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

Bae

Yoo

2014

IEICE Electron. Express

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A 3-Gbps decision feedback equalizer (DFE) compensating for data and edge inter-symbol interference (ISI) is presented. A speculative architecture is employed to relieve the timing burden on the feedback signal for the DFE wherein the ISI of edge sample is compensated by speculating the DFE based on two-UI earlier data sample. Thereby, the timing margins of the DFE for data and edge ISI compensation are ensured to be larger than 1.0-UI. The proposed DFE has been implemented in a 0.13-µm CMOS technology together with a clock and data recovery (CDR) circuit. The DFE and CDR circuits occupy 0.28-mm 2 active area and the DFE consumes 18-mW from a 1.2-V supply. The RMS jitter of the recovered clock is improved from 15.6-ps to 11.9-ps by the proposed edge ISI compensating DFE.

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Section: Introductionmentioning

confidence: 99%

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

Bae

Yoo

2014

IEICE Electron. Express

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“…Key limitations in meeting these requirements include channel characteristics and I/O power consumption. Even in short interconnects, the channel attenuation at very high data rates is significant, and using receiver equalization can greatly improve the link performance [1][2][3][4][5]. However, compensating a high level of loss requires many taps of equalization, which can significantly reduce the power efficiency of the link.…”

mentioning

confidence: 99%

“…Conventionally, analog taps of the equalizer are implemented using currentmode summers, thus the power consumption of the DFE increases proportionally with the number of taps. In the proposed architecture, a switched-capacitor S/H is employed to sample the input signal and combine it with the feedback coefficients at the front-end of the receiver [1], as shown in Fig. 25.6.2 (S/H/summer).…”

mentioning

confidence: 99%