A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

“…Since it increases the relative strength of the high-frequency components of the transmitted signals, crosstalk is also reduced [8]. Near-end channel equalisation is often implemented using finite impulse [9] 130 nm −12 dB (26″ FR4) 5 -1-tap -Balan et al [10] 130 nm −(40″ FR4) 6.4 2-tap 4-tap t L Wong et al [11] 9 0 n m −6.2 dB (10″ SMA) 6.0 -2-tap 10 −12 Park et al [12] 9 0 n m −12 dB (16″ Tyco) 7.0 -2-tap 10 −13 Leibowitz et al [13] 9 0n m −(18″ BP) −7.5 -10-tap 10 −12 Bulzacchelli et al [14] 9 0n m −33 dB (16″ Legacy BP) 10 4-tap 5-tap 10 −12 Hidaka et al [15] 9 0 n m −25.4 dB (29″ FR4) 10 response (FIR) filters that introduce zeros to offset the effect of the poles of the channels [45,46]. For example, the first-order pre-emphasis FIR filter shown in Fig.…”

A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE

“…Satisfying such a timing constraint is a difficult task in high speed systems. To mitigate this problem, several techniques have been reported in the literature including loop-unrolling (speculation) [7], soft decision [8], half-rate and quarter-rate architectures [8,9], and canceling the first post-cursor ISI tap in transmitter using FFE [10]. In loop-unrolling technique, instead of detecting the previous bits and then subtracting their ISI effect from the recent bit, first, the ISI effects of the previous bits for all possible scenarios are subtracted from the recent bit in parallel, and then one of the cases is selected based on the previous detected bits using a MUX [7].…”

“…The drawback of loop-unrolling technique is that by increasing the number of taps, area and power consumption grows exponentially, which is not suitable for low-power designs [6]. In CML logic based designs, soft decision technique in half-rate and quarter-rate architectures can be applied to relax the first feedback critical path [8]. In such systems, a latch (not a Flip-Flop) is used in the slicer block.…”

Minimum jitter adaptive decision feedback equalizer for 4PAM serial links

“…In [4], jitter information at the edges of data eyes is obtained by employing a set of temporally spaced samplers that sample the transition edge of the eyes at uniformly incremented time instants. The dualmode adaptive DFE proposed in [5] consists of a data DFE for maximizing the vertical opening of data eyes and a jitter DFE for minimizing the jitter at the edges of data eyes. In [6], a minimum jitter adaptive decision feedback equalizer was proposed for 2PAM serial links.…”