A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

Abstract

Abstract-A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER 10 12 was significantly increased with the use of DFE for short-to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally.

Device Requirements for Optical Interconnects to Silicon Chips

“…The best current results for transceivers are ~ 2.8 -6.5 pJ/bit for board or backplane interconnects [17], and ~ 2 pJ/bit [16] for moderate length chip-to-chip interconnects with a relatively ideal electrical channel. Other recent work shows receivers for such links with ~ 1 pJ/bit at ~10 Gb/s rates [51], [52]. Capacitively coupled proximity communication directly between chips allows particularly high densities of interconnections with similarly low energies [53], and there is a variety of other approaches also for dense short vertical "3-D" connections between chips or active circuit layers [54].…”

A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE

“…Therefore, the emulated n post-cursor ISI taps are noise free and in the summer block only ISI taps are canceled. This key point is the main advantage of DFE over analog equalizer [1,5,6].…”

“…In current-integrating based summer [12][13][14], the differential currents are integrated on the parasitic capacitors at the output node of the summer. In switched-capacitor based architecture [1,15], despite the previous two topologies, summation is performed by adding voltages and not currents, by using a sample-and-hold (S&H).…”

“…Specially, as the data rate per IO grows to 10 Gb/s and beyond, the limitations imposed by frequency dependent loss in the channel caused by dielectric loss and resistive loss, degrade signal-to-noise-ratio (SNR) in the receiver side by creating intersymbol interference (ISI). In addition, impedance discontinuities in the connectors and via stubs in the signal path, originate reflections and more ISI which further reduce SNR at the receiver side [1]. The other noise source that increases the noise level at the receiver side and affects SNR factor, is the crosstalk noise, which is caused by the aggressor channels and connectors.…”

Photonic switching devices based on semiconductor nano-structures

“…Additionally, there is a speed limitation for the electronic interconnection which typically employs millions of closely spaced metal wires in the state-of-the-art computer systems. Despite impressive advancements in the material and device technology, the current record of the onchip global interconnection lies at 5 Gb/s per channel [6] whilst the speed record of the chip-to-chip interconnection is at 10 Gb/s per channel [7]. A photonic switch that controls optical signals directly by another light beam with potential recovery times in the pico-or femto-second regimes has the capability for terahertz switching speed.…”