A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip

Abstract

Abstract-A 14.3-mm 2 code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

“…, the decoding process is finished with ˆn x as the decoder output; otherwise, repeat steps (1)(2)(3). If the decoding process doesn't end within predefined maximum number of iterations, max it , stop and output an error message flag and proceed to the decoding of the next data frame.…”

“…In TDMP, the block LDPC with j block rows can be viewed as concatenation of j layers or constituent sub-codes similar to observations made for AA-LDPC codes in [2]. In TDMP, after the check-node processing is finished for one block row, the messages are immediately used to update the variable nodes (2), whose results are then provided for processing the next block row of check nodes (1).…”

“…A memory can be used to store control inputs needed for different shifts in case of supporting one expansion factor [2], [15]. [2] uses Omega network, which is less complex than Benes network [15].…”

“…nz N = . So, the total savings in Q memory are 68% as a direct result of employing TDMP proposed in [2]. Instead of storing all the R messages, the compressed information cumulative sign, M1, -M1, +/-M2, and index of M1 is stored.…”

“…While fully-parallel LDPC decoder designs [6] suffered from complex interconnect issues, various semi-parallel implementations based on structured LDPC codes [2], [7]- [9], [13]- [14] alleviate the interconnect complexity. All the structured LDPC codes share the property that the H matrix is constructed out of cyclic shifted version of identity matrix and null matrices.…”