2007 IEEE International Conference on Communications 2007
DOI: 10.1109/icc.2007.750
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VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

Abstract: Abstract-We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2x when compared to the recent state-of-the-art decoder architectures.Index Terms-low-density parity-check (LD… Show more

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Cited by 74 publications
(38 citation statements)
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References 14 publications
(30 reference statements)
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“…Table II compares the implementation result of our decoder with existing 802.11n LDPC decoders from [3], [4], [6]. The solutions from [3], [4], [6] are all based on the conventional single-layer decoding architecture. As a fair comparison, the areas of those designs are all normalized to 45nm technology.…”
Section: Vlsi Implementation and Comparisonmentioning
confidence: 99%
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“…Table II compares the implementation result of our decoder with existing 802.11n LDPC decoders from [3], [4], [6]. The solutions from [3], [4], [6] are all based on the conventional single-layer decoding architecture. As a fair comparison, the areas of those designs are all normalized to 45nm technology.…”
Section: Vlsi Implementation and Comparisonmentioning
confidence: 99%
“…we can employ Z parallel check node processors to process Z rows in parallel. With this amount of parallelism, the conventional layered decoder can typically offer 100-1000 Mbps throughput [3], [4], [5], [6].…”
Section: Introductionmentioning
confidence: 99%
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“…In a semi-parallel implementation, memories are usually required to store the temporary results. In many practical systems, semi-parallel implementations are often used to achieve 100 Mbps to 1 Gbps throughput with reasonable complexity [7,21,35,42,43,54].…”
Section: Ldpc Decoder Accelerator Architecturementioning
confidence: 99%
“…In the literature, many efficient LDPC decoder VLSI architectures have been studied [6,9,12,14,18,24,27,29,35,37,39,45,47]. Turbo decoder VLSI architectures have also been extensively investigated by many researchers [5,8,20,21,25,30,33,41,44].…”
Section: Introductionmentioning
confidence: 99%