A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder implementations is mitigated by designing architecture-aware LDPC codes having embedded structural regularity features that result in a regular and scalable message-transport network with reduced control overhead. Second, the memory overhead problem in current day decoders is reduced by more than 75% by employing a new turbo decoding algorithm for LDPC codes that removes the multiple checkto-bit message update bottleneck of the current algorithm. A new merged-schedule merge-passing algorithm is also proposed that reduces the memory overhead of the current algorithm for low to moderate-throughput decoders. Moreover, a parallel soft-input-soft-output (SISO) message update mechanism is proposed that implements the recursions of the Balh-Cocke-Jelinek-Raviv (BCJR) algorithm in terms of simple "max-quartet" operations that do not require lookup-tables and incur negligible loss in performance compared to the ideal case. Finally, an efficient programmable architecture coupled with a scalable and dynamic transport network for storing and routing messages is proposed, and a full-decoder architecture is presented. Simulations demonstrate that the proposed architecture attains a throughput of 1.92 Gb/s for a frame length of 2304 bits, and achieves savings of 89.13% and 69.83% in power consumption and silicon area over state-of-the-art, with a reduction of 60.5% in interconnect length. Index Terms-Low-density parity-check (LDPC) codes, Ramanujan graphs, soft-input soft-output (SISO) decoder, turbo decoding algorithm, VLSI decoder architectures. I. INTRODUCTION T HE PHENOMENAL success of turbo codes [1] powered by the concept of iterative decoding via message-passing has rekindled the interest in low-density parity-check (LDPC) codes which were first discovered by Gallager in 1961 [2]. Recent breakthroughs to within 0.0045 dB of AWGN-channel capacity were achieved with the introduction of irregular LDPC codes in [3], [4] putting LDPC codes on par with turbo codes. However, efficient hardware implementation techniques of turbo decoders have given turbo codes a clear advantage Manuscript
Abstract-A 14.3-mm 2 code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.
With the exponential growth in Internet-of-Things (IoT) devices, security and privacy issues have emerged as critical challenges that can potentially compromise their successful deployment in many data-sensitive applications. Hence, there is a pressing need to address these challenges, given that IoT systems suffer from different limitations, and IoT devices are constrained in terms of energy and computational power, which renders them extremely vulnerable to attacks. Traditional cryptographic algorithms use a static structure that requires several rounds of computations, which leads to significant overhead in terms of execution time and computational resources. Moreover, the problem is compounded when dealing with multimedia contents, since the associated algorithms have stringent QoS requirements. In this paper, we propose a lightweight cipher algorithm based on a dynamic structure with a single round that consists of simple operations, and that targets multimedia IoT. In this algorithm, a dynamic key is generated and then used to build two robust substitution tables, a dynamic permutation table, and two pseudo-random matrices. This dynamic cipher structure minimizes the number of rounds to a single one, while maintaining a high level of randomness and security. Moreover, the proposed cipher scheme is flexible as the dimensions of the input matrix can be selected to match the devices' memory capacity. Extensive security tests demonstrated the robustness of the cipher against various kinds of attacks. The speed, simplicity and high-security level, in addition to low error propagation, make of this approach a good encryption candidate for multimedia IoT devices.
Cell-free massive MIMO communications is an emerging network technology for 5G wireless communications wherein distributed multi-antenna access points (APs) serve many users simultaneously. Most prior work on cell-free massive MIMO systems assume time-division duplexing mode, although frequency-division duplexing (FDD) systems dominate current wireless standards. The key challenges in FDD massive MIMO systems are channel-state information (CSI) acquisition and feedback overhead. To address these challenges, we exploit the socalled angle reciprocity of multipath components in the uplink and downlink, so that the required CSI acquisition overhead scales only with the number of served users, and not the number of AP antennas nor APs. We propose a low complexity multipath component estimation technique and present linear angle-ofarrival (AoA)-based beamforming/combining schemes for FDDbased cell-free massive MIMO systems. We analyze the performance of these schemes by deriving closed-form expressions for the mean-square-error of the estimated multipath components, as well as expressions for the uplink and downlink spectral efficiency. Using semi-definite programming, we solve a maxmin power allocation problem that maximizes the minimum user rate under per-user power constraints. Furthermore, we present a user-centric (UC) AP selection scheme in which each user chooses a subset of APs to improve the overall energy efficiency of the system. Simulation results demonstrate that the proposed multipath component estimation technique outperforms conventional subspace-based and gradient-descent based techniques. We also show that the proposed beamforming and combining techniques along with the proposed power control scheme substantially enhance the spectral and energy efficiencies with an adequate number of antennas at the APs.Index Terms-FDD mode, cell-free massive MIMO, multipath component estimation, array signal processing, angle-based beamforming/combining, power control.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.