A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers

Abstract

A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18µm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.Introduction Performing accurate, power efficient amplification in scaled CMOS technologies remains a persistent and pressing challenge. Reduced supply voltages and intrinsic device gains exacerbate the accuracy/power trade-off imposed by the deleterious effects of finite amplifier gain error. Many effective solutions to this problem have been developed -ranging from analog gain-enhancement techniques, digital correction schemes, and even altogether new amplification paradigmsbut the solutions often come with a penalty in the classic speed/power/accuracy tradeoff relationship. Furthermore, the operational paradigm for most amplifier implementations remains based on RC-type settling, which when driving large capacitive loads, benefits little from process scaling (i.e. power-delay product improvements). In other words, most existing approaches to scalable amplification work by masking the symptoms of the disease rather than actually curing it. To cure such a problem, an entirely new amplification paradigm is required -one which is inherently suited to operate in modern and future scaled environments.Ring Amplification This paper explores the concept and practical application of ring amplification. The basic structure of a ring amplifier (alternately: ring amp, RAMP) is shown in Fig. 1, and is the actual transistor-level implementation used in the ADC presented in this paper. The ring amp is effectively a ring oscillator whose input signal takes two separate paths to the output (in fact, for V RP = V RN , it is functionally equivalent to a 3-inverter ring oscillator). When V RP > V RN , the capacitors C 2 and C 3 will embed different voltage offsets in each signal path such that for a certain range of input values, neither M P3 nor M N3 will conduct. As seen in Fig. 2, this non-conduction region, or dead-zone, creates plateaus in the output (and input) waveforms of the amplifier as it oscillates. These plateaus reduce the average gain of the amplifier, and for a sufficiently large dead-zone, the average gain will be reduced enough that the unity-gain frequency now corresponds to a phase shift of less than 180°. When this criterion is met, the oscillator will begin to stabilize and settle. This will occur very quickly (much quicker than the "teaching" example of Fig. 2) due to two key feedback mechanisms which continue to dynamically reduce the effective gain of the ring amplifier (and thus increase phase margin and stability). The first mechanism is due to the fact V IN V OUT V RN Φrst Φrst Φrst V RP 840nm 160nm 840nm 160nm 320nm 160...

A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers

“…Table II compares the performance of the prototype ADC with conventional ring amplifier based ADCs. This work achieves a three times better FoM (with Nyquist frequency input) than [9] which uses the same 1.5 b/stage ADC structure. In addition, the FoM of the prototype ADC is better than or comparable to more energy effective structured ADCs [8], [11].…”

“…26 compares the FOM with pipeline ADCs presented at ISSCC (1997-2015) and the VLSI Symposium (1997-2014) [18]. The FOMs of [8] and [9] are updated with the Nyquist frequency input values for a fair comparison. Excluding the IEEE JOURNAL OF SOLID-STATE CIRCUITS SAR-assisted pipeline ADCs which have a more efficient hybrid SAR and pipeline ADC architecture [19], this work has a state-of-the-art FOM among the pipeline ADCs.…”

“…However, we still need to consider the device to device variation which can cause large output common mode variation. The device to device variation is particularly problematic since the ring amplifier uses almost minimum sized transistors [9].…”

“…We can eliminate SHA as in[9] if we use a conventional flash ADC for the first stage sub-ADC. The elimination of SHA also improves SNR and power efficiency of the ADC since the SHA adds noise to the sampled input signal without providing amplification.…”

Emerging analog-to-digital converters

“…The ringamp operating speed is limited by the oscillation speed in a given technology node, leading to speed/accuracy trade-off as in most analog circuits. However, the simplistic nature of the building blocks is expected to be more scalable with technology [16]. Other more recent implementations have shown very strong figure-of-merit results [17], [18].…”