A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

Zhao, Dixian; Reynaert, Patrick

doi:10.1109/jssc.2013.2275662

Cited by 208 publications

(86 citation statements)

References 28 publications

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“…Our PA achieves comparable BW −3dB as in a 28 nm PA [4], but with a much higher PAE. For P sat ≈18 dBm, only class-AB PA in [6] shows better PAE, but at a lower gain and BW. Furthermore, the product of PAE and BW reaches the best reported.…”

Section: Measurement Resultsmentioning

confidence: 99%

A wideband 60 GHz class-E/F<inf>2</inf> power amplifier in 40nm CMOS

Babaie

Staszewski

Galatro

et al. 2015

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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Section: Measurement Resultsmentioning

confidence: 99%

A wideband 60 GHz class-E/F<inf>2</inf> power amplifier in 40nm CMOS

Babaie

Staszewski

Galatro

et al. 2015

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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“…The transistor unit has a total dimension of 178µm/40nm. The local transistor layout in [4] is adopted to reduce the device parasitics, and M1-M3 layers are used for local ground to reduce the IR drop. The ground planes connect to the degeneration inductors from both sides.…”

Section: Circuit Implementationmentioning

confidence: 99%

A high-efficiency linear power amplifier for 28GHz mobile communications in 40nm CMOS

Zhang

Reynaert

2017

2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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Abstract-This paper presents a high-efficiency, linear power amplifier (PA) for 28GHz mobile communications in 40nm CMOS technology. The design and layout are optimized for high linearity while maintaining high gain and output power. A capacitance neutralized differential pair with source degeneration inductor for linearity enhancement is discussed. The inductive degeneration technique greatly increases the optimal load impedance, which enables a low loss parallel power combining. The complete PA achieves a measured saturated output power of 18.1dBm with 41.5% power-added efficiency (PAE). With 6 Gb/s QAM-64 signals, the proposed PA achieves an average output power of 8.4dBm and 8.8% PAE, with -25 dBc EVM. All measurements are performed with a fixed bias condition.Index Terms-CMOS, power amplifier, inductive degeneration, linearity, EVM, 5G. I. INTRODUCTIONSeveral frequency bands in millimeter-wave (mmWave) range have been licenced for future fifth generation (5G) wireless communication systems, enabling Gb/s data rate with low latency. To meet the demand of large data traffic within limited spectrum resources, high order modulation scheme like 64 QAM will be adopted, which presents large peak-to-average power ratio (PAPR).To amplify these modulated signals with high fidelity, PA designs for 5G applications have to meet the stringent AM-AM and AM-PM linearity requirements. In RF and microwave range, multiple correction techniques have been investigated to improve linearity of the front-ends. However, it is challenging to deploy these techniques into 5G applications, such as phased arrays and MIMO systems, where the baseband bandwidth is relatively large and the function units might be distributed into the systems. Digital pre-distortion (DPD) for each PA can be prohibitively complex for large-scale arrangement. In any case, the nonlinearity property of the PA itself needs to be dealt with in the first place.Recently, lots of efforts have been put to improve the PA performance for 5G applications. In the work of [1], high efficiency and linearity are achieved by using subthreshold biasing and inductive degeneration. And as a variable, the size of the transistor is optimized for -25dBc EVM. In [2], the linearity is greatly improved by using second harmonic control and deep class-AB biasing. However, the overall performance of the PA, in terms of

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“…2) Power Amplifier: Fig.7b presents the schematic of the power amplifier (PA), which incorporates 3-stage differential transformer-coupled topology with capacitive cross-coupled neutralization for stabilization [22], [23]. The PA design essentially involves three key aspects, namely the active devices, the impedance matching network, and the stabilization method.…”

Section: ) Digital Building Blocksmentioning

confidence: 99%

A mm-Precise 60 GHz Transmitter in 40 nm CMOS for Discrete-Carrier Indoor Localization

Indirayanti

Ayhan

Verhelst

et al. 2015

IEEE J. Solid-State Circuits

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This paper presents a multicarrier 60GHz transmitter for distance measurement (ranging) in an indoor wireless localization system, achieving mm-precision with high update rate. The architecture comprises a baseband subcarrier generator, an upconverter, and a power amplifier. There are three key innovations, all stemming from careful hardware-algorithm co-design: 1. efficient frequency planning of the 6GHz-wide band; 2. power-efficient multicarrier signal generation by means of digital frequency divisions exploiting the phase-based time-of-arrival ranging algorithm; and 3. PAPR reduction to enable efficient operation of the power amplifier. By implementing these key techniques, 0.7-2.7mm precision is achieved over 5m measured distance with 5.4µs symbol duration. During operation, the core digital subcarrier generator generates 16 non-equidistant subcarriers from a 3GHz input clock, while consuming an average power of 1.8mW out of 0.9V supply. The upconverter and the power amplifier altogether consume around 127mW. The total area of the transmitter is 1.1mm2 . The chip is fabricated in a 40nm general purpose CMOS process.P. Indirayanti, T. Ayhan, M. Verhelst, W. Dehaene, and P. Reynaert are with the MICAS Division, Departement of Electrical Engineering (ESAT), KU Leuven,

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A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

Cited by 208 publications

References 28 publications

A wideband 60 GHz class-E/F<inf>2</inf> power amplifier in 40nm CMOS

A wideband 60 GHz class-E/F<inf>2</inf> power amplifier in 40nm CMOS

A high-efficiency linear power amplifier for 28GHz mobile communications in 40nm CMOS

A mm-Precise 60 GHz Transmitter in 40 nm CMOS for Discrete-Carrier Indoor Localization

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