A wideband 60 GHz class-E/F&lt;inf&gt;2&lt;/inf&gt; power amplifier in 40nm CMOS

Babaie, Masoud; Staszewski, Robert Bogdan; Galatro, L.; Spirito, M.

doi:10.1109/rfic.2015.7337743

Cited by 20 publications

(9 citation statements)

References 5 publications

(10 reference statements)

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“…Other technologies such as GaAs HBT and GaN are able to report higher efficiencies and output power on the expense of cost and integration capabilities such as in [4], [13] at lower frequency bands. Overall, we are able to report the best performance at RF frequencies as high as 28 GHz compared to similar work reporting compatible efficiencies at 2.25 GHz in [10], [11] and better efficiency compared to other switching PAs near 28 GHz in [18]- [20]. To the best of our knowledge, no other work in literature reports similar performance at similar frequency bands.…”

Section: A Comparison With State-of-the-art Cmcd Passupporting

confidence: 63%

A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

et al. 2020

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Current Mode Class-D (CMCD) Power Amplifiers are of particular interest in outphasing transmitters or Doherty configuration. This is because the output capacitance can be absorbed in the RLC output matching network and 100% theoretical efficiency. In this paper, a 28 GHz current mode (inverse) Class-D power amplifier was simulated, implemented, and measured in 22nm FDSOI. In order to overcome the breakdown voltages of the devices, the amplifier employs a stacked topology, which enables higher output powers and efficiency. The stacked transistors are also pulse injected to further increase the efficiency. Measurement results shows a peak PAE of 46%, peak drain efficiency (DE) of 71% and a saturated output power of 19 dBm. The implemented CMCD PA reports the best performance in literature compared to other CMOS based CMCD PAs.INDEX TERMS Current mode class-D, FDSOI CMOS, high efficiency, power added efficiency (PAE), power amplifier (PA), stacking.

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Section: A Comparison With State-of-the-art Cmcd Passupporting

confidence: 63%

A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

et al. 2020

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“…Unfortunately, as can be gathered from (20), the voltage summation (m > 1) and imperfect magnetic coupling k m exhibit reverse effect of reducing r L . The p-way current combining enhances r L but at the price of (p − 1) extra transformers and thus a dramatic increase in the PA die area [43], [44]. Hence, the parallel combining is not considered in this work.…”

Section: B Impedance Transformationmentioning

confidence: 99%

“…Dsat represents the transistor's average V DS in the on-state. As explained in [44], V Dsat is a strong function of the switch size, technology and topology-dependent parameters, and it is set to ∼0.12 V to maximize the PAE of the proposed PA. The shunt capacitance, C s , and series inductance, L ser , may be estimated by exploiting K c and K L definitions:…”

Section: Class-e/f 2 Operationmentioning

confidence: 99%

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

Babaie

Kuo

Chen

et al. 2016

IEEE J. Solid-State Circuits

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We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

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“…An efficient power-competing technique is crucial to achieving an output power of 20 dBm requirement without sacrificing power-added efficiency (PAE). The power combiner could be implemented by quarter-wavelength transmission lines (TL) or transformer (TF) [7]. Those two methods could achieve a wideband impedance match in this frequency band.…”

Section: Power Combiner Considerationmentioning

confidence: 99%

A 77 GHz Power Amplifier Design with in-Phase Power Combing for 20 dBm P_sat in a 40-nm CMOS Technology

Zhang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Detection distance is a critical specification in automotive driving. The output power of a power amplifier is the bottleneck for the detection range. In this work, a design of 77 GHz power amplifier is presented in a 40 nm CMOS technology with a four-way parallel-series power combing technique for achieving a 20 dBm output power (Psat), which meets a 186-meter detection range in the conditional of 30 mm/h rainfall capacity. In this parallel-series power combing technique, distributed active transformers perform load-pull matching and in-phase power combining. It achieves a compact solution for future on-chip antenna integration. This PA is optimized for maximal power-added efficiency of 21.35% with 20 dBm saturated output power at 77 GHz.

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A wideband 60 GHz class-E/F<inf>2</inf> power amplifier in 40nm CMOS

Cited by 20 publications

References 5 publications

A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

A 77 GHz Power Amplifier Design with in-Phase Power Combing for 20 dBm P_sat in a 40-nm CMOS Technology

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A wideband 60 GHz class-E/F<inf>2</inf> power amplifier in 40nm CMOS

Cited by 20 publications

References 5 publications

A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

A 77 GHz Power Amplifier Design with in-Phase Power Combing for 20 dBm Psat in a 40-nm CMOS Technology

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A 77 GHz Power Amplifier Design with in-Phase Power Combing for 20 dBm P_sat in a 40-nm CMOS Technology