A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

Elsayed, Nourhan; Saleh, Hani; Mohammad, Baker; Sanduleanu, Mihai

doi:10.1109/access.2020.2996907

Cited by 6 publications

(4 citation statements)

References 23 publications

(18 reference statements)

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“…However, the cut-off frequency (f T ) of the used process technology is in the hundreds of GHz, allowing realization of quantum gate flip operations <50 ps, which is 2-3 orders of magnitude faster than with the spin counterparts. In further support of the process capabilities, [57], [58] disclose measurement results of digital and mixedsignal circuits, also implemented in the same 22-nm FD-SOI, indicating that the circuits can be functionally faster than 50 ps, i.e., equivalent to 20 GHz operating speed.. This suggest roughly the same number of over 1000 gate operations per useful decoherence time.…”

Section: Qubit Interface Circuitrymentioning

confidence: 83%

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

Staszewski

Esmailiyan²,

Wang

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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We present a fully integrated cryogenic controller for electrostatically controlled quantum dots (QDs) implemented in a commercial 22-nm FD-SOI CMOS process and operating in a quantum regime. The QDs are realized in local well areas of transistors separated by tunnel barriers controlled by voltages applied to gate terminals. The QD arrays (QDA) are co-located with the control circuitry inside each quantum experiment cell, with a total of 28 of such cells comprising this system-on-chip (SoC). The QDA structure is controlled by small capacitive digital-to-analog converters (CDACs) and its quantum state is measured by a single-electron detector.The SoC operates at a cryogenic temperature of 3.4 K. The occupied area of each QD array is 0.7×0.4 µm 2 , while each QD occupies only 20×80 nm 2 . The low power and miniaturized area of these circuits are an important step on the way for integration of a large quantum core with millions of QDs, required for practical quantum computers. The performance and functionality of the CDAC are validated in a loop-back mode with the detector sensing the CDAC-compelled electron tunneling from the quantum point contact (QPC) node into the quantum structure. Position of the injected charge inside the QD array is intended to be controlled through the CDAC codes and programmable pulse width. Quantum effects are shown by an experimental characterization of charge injection and quantization into the QD array consisting of three coupled QDs. The charge can be transferred to a QD and sensed at the QPC, and this process is controlled by the relevant voltages and CDACs.Index Terms-Capacitive DAC (CDAC), charge qubits, cryo-CMOS, fully depleted silicon-on-insulator (FD-SOI), imposer, positionbased qubits, quantum computer (QC), quantum dot (QD), single-electron detector, single-electron injector. I. INTRODUCTIONQ UANTUM computing is a new paradigm that utilizes the fundamental principles of quantum mechanics, such as superposition, interference and entanglement [1], [2]. The range of complex problems from mathematics, chemistry and material science that could be solved with quantum computing is far beyond the reach of today's most powerful supercomputers. The potential is thus immense. Quantum bits (qubits), basic units of quantum information, operate at a molecular/atomic level. They are extremely fragile and difficult to manipulate and read out. Some quantum computer technologies, such as based on trapped ions and photons, do not require the equipment to be cryogenically cooled [3], [4], but the majority of qubits must operate under extremely low Manuscript received

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Section: Qubit Interface Circuitrymentioning

confidence: 83%

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

Staszewski

Esmailiyan²,

Wang

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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“…It employs a main amplifier (Class-AB) and an auxiliary amplifier (switched cascode Class-E). A standalone version of this PA has been implemented and described in [ 8 ].…”

Section: Phased Array Transmittermentioning

confidence: 99%

A 28 GHz Phased-Array Transceiver for 5G Applications in 22 nm FD-SOI CMOS

Cracan¹,

Elsayed

Sanduleanu

2023

Micromachines

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This paper presents the design and implementation of a 28 GHz phased array transceiver for 5G applications using 22 nm FD-SOI CMOS technology. The transceiver consists of a four-channel phased array receiver and transmitter, which employs phase shifting based on coarse and fine controls. The transceiver employs a zero-IF architecture, which is suitable for small footprints and low power requirements. The receiver achieves a 3.5 dB NF with a 1 dB compression point of −21 dBm and a gain of 13 dB.

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“…Micromachines 2023, 14, x FOR PEER REVIEW 2 of 10 [15,16], current-combining transformers [17], direct combining, pulse injection [18], and Doherty topology [19]. This paper proposes a D-band LNA and PA for vital-signs-monitoring systems.…”

Section: System Architecturementioning

confidence: 99%

“…The speed limitations of CMOS devices make it challenging to implement sub-millimeter-wave PAs. Several techniques have been proposed to address these challenges, including capacitive neutralization [ 15 , 16 ], current-combining transformers [ 17 ], direct combining, pulse injection [ 18 ], and Doherty topology [ 19 ].…”

Section: Introductionmentioning

confidence: 99%

160 GHz D-Band Low-Noise Amplifier and Power Amplifier for Radar-Based Contactless Vital-Signs-Monitoring Systems

Mustapha

Sanduleanu

2023

Micromachines

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This paper presents a 160 GHz, D-band, low-noise amplifier (LNA) and a D-band power amplifier (PA) implemented in the Global Foundries 22 nm CMOS FDSOI. The two designs are used for the contactless monitoring of vital signs in the D-band. The LNA is based on multiple stages of a cascode amplifier topology with a common source topology adopted as the input and output stages. The input stage of the LNA is designed for simultaneous input and output matching, while the inter-stage-matching networks are designed for maximizing the voltage swing. The LNA achieved a maximum gain of 17 dB at 163 GHz. The input return loss was quite poor in the 157–166 GHz frequency band. The −3 dB gain bandwidth corresponded to 157–166 GHz. The measured noise figure was between 7.6 dB and 8 dB within the −3 dB gain bandwidth. The power amplifier achieved an output 1 dB compression point of 6.8 dBm at 159.75 GHz. The measured power consumptions of the LNA and the PA were 28.8 mW and 10.8 mW, respectively.

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A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

Cited by 6 publications

References 23 publications

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

A 28 GHz Phased-Array Transceiver for 5G Applications in 22 nm FD-SOI CMOS

160 GHz D-Band Low-Noise Amplifier and Power Amplifier for Radar-Based Contactless Vital-Signs-Monitoring Systems

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