A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

Abstract

Summary This paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm.

A charge sharing–based switching scheme for SAR ADCs

“…However, as can be seen from Figure 1, despite a decrease in the number of the capacitors and switches compared with the charge recycling scheme presented in Hu et al, 11 the proposed switching scheme needs still different switches that should be turned on during each transition. Therefore, based on Equation (2), averaging process reduces the standard deviation of the capacitor mismatch as follows 14,15 : In order to decrease the effect of such nonidealities, the proposed switching scheme can be designed using the scaled-down Complementary metal-oxide-semiconductor (CMOS) technologies under a supply voltage around 1 V. Figure 1 shows that unary weighted capacitors are employed for N > 3 to configure the capacitor arrays making the design more robust to the systematic mismatch.…”

“…[1][2][3] To this end, several switching schemes such as monotonic, 4 high-accuracy, 5 tri-level, 6 common-mode voltage (V CM )-based, 7 hybrid, 8 dual-capacitor, 9 energy-efficient, 10 and charge recycling-based 11,12 techniques have been recently presented to improve the accuracy and the power efficiency of the capacitive DACs. However, the capacitor arrays of the digital-to-analogue converter (DAC) blocks consume the most power in comparison with the comparator and the digital control logic.…”

Shifting the sampled input signal in successive approximation register analog‐to‐digital converters to reduce the digital‐to‐analog converter switching energy and area

“…In charge‐redistribution SAR ADCs, the power consumption of the capacitor switching in the digital‐to‐analog converter (DAC) usually is dominant 1–5,9–15 . Recently, several techniques have been presented to reduce the DAC switching energy and capacitor size 1–26 …”

Four innovative calibration algorithms for capacitive mismatch in 18‐bit redundant split SAR ADC

“…For simplicity, Figure 1 shows the basic block diagram for an 8‐bit SAR ADC, which includes a differential capacitive digital‐to‐analog converter (DAC) array, a comparator, and a SAR control logic. Obviously, SAR ADCs are much simpler and more power‐efficient than other types of ADC such as pipeline‐ADCs by avoiding the high bandwidth amplifiers 1‐9 …”