A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

Wang, Dengjie; Wang, Ziqiang; Xu, Hao; Wang, Jiawei; Zhao, Ziqiang; Zhang, Chun; Wang, Zhihua; Chen, Hong

doi:10.1109/tcsi.2021.3125355

Cited by 11 publications

(7 citation statements)

References 32 publications

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“…7. Meeting critical timing margins is a challenging part of the DFE architecture, for which we employ a half-rate speculative structure to obtain the first-Tap timing requirement [23,24,25]. Compared to the traditional structure, the DFE speculatively adds and subtracts the tap coefficient C 1 within the sampling phase of the slicer, then selects two outputs based on the previous one-bit decision, which avoids tight timing constraints.…”

Section: -Tap Half Rate Dfe With Speculative Tapmentioning

confidence: 99%

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Zhu

Chu

2023

IEICE Electron. Express

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This work proposes a RX front-end structure, which is used for channel equalization of 25 Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19 dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005 mm 2 designed in 65 nm CMOS, the power consumption of which is 96 mW under 1.2 V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35 dB at 12.5 GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171 mV and 0.61 UI at the BER of 10 −12 , respectively.

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Section: -Tap Half Rate Dfe With Speculative Tapmentioning

confidence: 99%

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Zhu

Chu

2023

IEICE Electron. Express

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“…The latched comparator is a key building block for many mixed-signal applications, and finds wide diffusion in systems such as analog-to-digital converters (ADCs), wireline receivers, memory bit-line detectors and digital low-dropout regulators (DLDOs) [3,[7][8][9][10][11]. The comparator is usually composed of an input preamplifier followed by a latch, often combined in the StrongARM topology [12][13][14], where a clocked transconductor drives a pair of cross-coupled inverters by their sources or, in the double-tail topology [15][16][17][18], where the clocked preamplifier and the latch use separate tail current branches.…”

Section: Introductionmentioning

confidence: 99%

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

Della Sala,

Centurelli,

Scotti

et al. 2023

Chips

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This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologies is introduced. Then, a set of simulation testbenches are defined in order to simulate and compare the considered topologies implemented in both a 130 nm technology and a 28 nm FDSOI CMOS process. Propagation delay, power consumption and power–delay product are evaluated for different values of the input common mode voltage, as a function of input differential amplitude, and in different supply voltage and temperature conditions. Monte Carlo simulations to evaluate the input offset voltage under mismatch variations are also provided. Simulation results show that the performances of the different comparator topologies are strongly dependent on the input common mode voltage, and that the best values for all the performance figures of merit are achieved by the comparator based on three-input NAND gates, with the only limitation being its non-rail-to-rail input common mode range (ICMR). The performances of the considered comparator topologies have also been simulated for different values of the supply voltage, ranging from 0.3 V to 1.2 V, showing that, even if standard-cell-based comparators can be operated at higher supply voltages by scaling their performances accordingly, the best values of the FoMs are achieved for VDD = 0.3 V.

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“…However, the main drawback of the current‐mode logic (CML) circuits is their high static power consumption due to the presence of a constant current source 23–25 . In addition, in CML hybrid circuit implementations, a time constant (RC) is created by a product of the load resistance and load capacitance that decides the speed and bandwidth of the CML circuit 26,27 . A small load resistance value can decrease the RC time‐constant for settling time.…”

Section: Introductionmentioning

confidence: 99%

“…A small load resistance value can decrease the RC time‐constant for settling time. However, reducing the load resistance value reduces the hybrid gain, voltage swing, and increase in the current consumption resulting in a power penalty 26,27 . Hence, it is challenging to design a power‐efficient hybrid in FD signaling at a low bit‐error‐rate (BER).…”

Section: Introductionmentioning

confidence: 99%

“…[23][24][25] In addition, in CML hybrid circuit implementations, a time constant (RC) is created by a product of the load resistance and load capacitance that decides the speed and bandwidth of the CML circuit. 26,27 A small load resistance value can decrease the RC time-constant for settling time. However, reducing the load resistance value reduces the hybrid gain, voltage swing, and increase in the current consumption resulting in a power penalty.…”

Section: Introductionmentioning

confidence: 99%

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A power‐efficient current‐integrating hybrid for full‐duplex communication over chip‐to‐chip interconnects

Govindaswamy

Pasupureddi

2022

Circuit Theory & Apps

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This work proposes a power-efficient half-rate current-integrating logic (CIL) echo cancelation hybrid circuit topology for full-duplex communication for off-chip interconnects in 65 nm CMOS. The proposed hybrid topology has a low power consumption compared to traditional current-mode hybrid circuit topology implementations, thanks to the CIL hybrid topology with sample and hold front-end. The post-layout performance of the half-rate CIL hybrid includes package parasitic has a differential received signal voltage swing of 190 mV at 10 Gb/s data rate with a timing jitter of 16 ps over a 20 cm FR4 PCB interconnect. The total power consumption of the half-rate CIL hybrid is only 2 mW, and its energy efficiency is 0.4 pJ/bit. The layout of the hybrid occupies an area of 0.0008 mm 2 .

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A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

Cited by 11 publications

References 32 publications

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

A power‐efficient current‐integrating hybrid for full‐duplex communication over chip‐to‐chip interconnects

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