A power‐efficient current‐integrating hybrid for full‐duplex communication over chip‐to‐chip interconnects

Abstract

This work proposes a power-efficient half-rate current-integrating logic (CIL) echo cancelation hybrid circuit topology for full-duplex communication for off-chip interconnects in 65 nm CMOS. The proposed hybrid topology has a low power consumption compared to traditional current-mode hybrid circuit topology implementations, thanks to the CIL hybrid topology with sample and hold front-end. The post-layout performance of the half-rate CIL hybrid includes package parasitic has a differential received signal voltage swing of 190 mV at 10 Gb/s data rate with a timing jitter of 16 ps over a 20 cm FR4 PCB interconnect. The total power consumption of the half-rate CIL hybrid is only 2 mW, and its energy efficiency is 0.4 pJ/bit. The layout of the hybrid occupies an area of 0.0008 mm 2 .

An adaptive link training based hybrid circuit topology for full‐duplex on‐chip interconnects

“…[3][4][5] Further, the full-duplex signaling scheme is preferred over unidirectional signaling techniques for energy-efficient data transmission over lossy on-chip global interconnect. In a full-duplex signaling scheme, the link throughput is doubled by having data flow in both directions simultaneously 4,[6][7][8][9][10][11][12] as shown in Figure 1. However, the major issue with the full-duplex signaling scheme is the formation of a superimposed signal which is a combination of both outgoing and incoming signal.…”