A 55 ns 0.35 μm 5 V-only 16 M flash memory with deep-power-down

Venkatesh, B.; Chung, Michelle; Govindachar, S.; Santurkar, V.; Bill, C.; Gutala, Ravi; Zhou, Deng; Yu, Jungeun; Buskirk, Michael Van; Kawamura, Shingo; Kurihara, Kenji; Kawashima, Hiroshi; Watanabe, H.

doi:10.1109/isscc.1996.488507

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Cited by 7 publications

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“…Recently, many Flash memories utilize a negative-gate erase scheme [1], [10]. In particular, this erase scheme is suitable for a single voltage supply Flash memory, because it realizes lower power consumption in erase mode than a source erase scheme.…”

Section: Level Shifter Circuitmentioning

confidence: 99%

Circuit techniques for 1.5-V power supply flash memory

Otsuka

Horowitz

1997

IEEE J. Solid-State Circuits

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We describe circuit techniques for a Flash memory which operates with a V DD of 1.5 V. For the interface between the peripheral circuits and the memory core circuits, two types of level shifter circuits are proposed which convert a V DD level signal into the high voltage signals needed for high performance. In order to improve the read performance at a low V DD , a new self-bias bitline voltage sensing scheme is described. This circuit greatly reduces the delay's dependence on bitline capacitance and achieves 19 ns reduction of the sense delay at low voltages. Multilevel storage sensing with this circuit is also discussed.

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Section: Level Shifter Circuitmentioning

confidence: 99%