A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

Umezawa, Akira; Atsumi, S.; Kuriyama, M.; Banba, H.; Imamiya, K.; Naruke, K.; Yamada, Shigeru; Obi, E.; Oshikiri, M.; Suzuki, Toshihiro; Tanaka, S.

doi:10.1109/4.165334

Cited by 137 publications

(56 citation statements)

References 3 publications

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“…Fig. 9 illustrates the proposed charge-pump configuration, which is based on the conventional pump proposed in [13], and to which only several logic circuits and PC2 switches are added. For simplicity, the figure shows the charge-pump circuit which outputs 4.5 V with two pumps in read operation and 10 V with a single pump in program operation.…”

Section: Charge-pump Circuitmentioning

confidence: 99%

Circuit techniques for a 1.8-V-only NAND flash memory

Tanzawa

Tanaka

Takeuchi

et al. 2002

IEEE J. Solid-State Circuits

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Abstract-Focusing on internal high-voltage () switching and generation for low-voltage NAND flash memories, this paper describes a switch, row decoder, and charge-pump circuit. The proposed nMOS switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 A. The proposed pump scheme reduced the area required for charge-pump circuits by 40%.Index Terms-Charge-pump circuit, high-voltage switching, low supply voltage, NAND flash memories, row decoder.

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Section: Charge-pump Circuitmentioning

confidence: 99%

Circuit techniques for a 1.8-V-only NAND flash memory

Tanzawa

Tanaka

Takeuchi

et al. 2002

IEEE J. Solid-State Circuits

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“…This facilitates higher charge transfer for subsequent stages. This concept of augmenting internal node voltages > V DD has been demonstrated in Flash memories (Umezawa et al, 1992;Atsumi et al, 1994). The Bootstrap CP (Fig.…”

Section: Bootstrap Charge Pumpmentioning

confidence: 99%

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Mi¹,

Islam

Sampe

et al. 2016

American Journal of Applied Sciences

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This paper reviews CMOS based charge pump topologies used within autonomous embedded micro-systems. These charge pump structures have evolved from its simplistic diode-tied, single-branches with major threshold drops to exponential type, dual-branches with sophisticated gate and substrate control for lower voltage operation. Published charge pumps are grouped based on architecture, operation principles and pump optimization techniques with their pros and cons compared and results contrasted. The various charge pump topologies and schemes used are considered based on pumping efficiency, power efficiency, charge transferability, circuit complexity, pumping capacitors, form factor and minimum supply voltages with an optimum load. This article concludes with an overview of suitable techniques and recommendations that will aid a designer in selecting the most suitable charge pump topology especially for low ambient micro energy harvesting applications.

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“…The Gummel and Poon model is reduced further to the effects that are relevant for the forward-biased transistor. The leakage currents are ignored too, because in modern IC processes these leakage currents are negligibly small [8]. It is assumed that the transistor is biased far from highlevel injection.…”

Section: The Key Parameters Of the Gummel And Poon Modelmentioning

confidence: 99%